fpga - Reset: synchronous vs asynchronous

I've been working with fpgas for years, and always used synchronous resets for every parts (that need it) of my circuits. It helps the circuit to be globally reset at a given clock cycle.

However, I was told that in ASIC circuits, people tend to use asynchronous reset everywhere. I'm wondering why, and if it is the case in some fpga designs too. I would love to hear professional opinions.

Thanks

Answer

There seem to be a lot of views on this one.
Asynchronous assertion, synchronous deassertion is said to be good practice. This avoids the issue of the clock not running (or running too slowly to capture the reset signal) on synchronous assertion, and possible metastability on asynchronous deassertion.

You would use a reset synchroniser (two FFs) with the output tied to the rest of the designs resets:

Couple of discussions:
Async and sync reset
Letters On Sync vs. Async Resets