pcb design - Should I really divide the ground plane into analog and digital parts?

I am about to design my first PCB as part of my graduation project. Of course, as the first step, I try to learn as much as possible. A part of the research I found this 3 part article, that suggests that it is not neccessary and in some cases is even harmful to split the ground plane into analog and digital part, which contradicts what I had learned from the prof. I also read all threads on this site that are concerned with the ground planes/pours. Although majority concur with the article, there are still some opinions that advocate split ground plane. eg

https://electronics.stackexchange.com/a/18255/123162 https://electronics.stackexchange.com/a/103694/123162

As a PCB design novice, I find it confusing and hard to decide who is right and which approach to take. So, should I divide the ground plane into analog and digital parts? I mean physical division, either with a PCB cut or having separate polygons for DGND and AGND (either not connected, or connected in one point)

Perhaps to enable you to make a recommendation, that is tailored to my prospective PCB, I tell you about it.

The PCB will be designed in the free version of Eagle=> 2 layers

The PCB is for testing and precise measurement (current & voltage) of lithium batteries. The board is to be controled from Raspberry Pi over digital interface (GPIO/SPI (40 kHz)). There will be 3 data converters on board (AD5684R, MAX5318, AD7175-2),and connectors for a prebuilt RTC module on the digital side. Analog power comes from external regulated power supply over onboard LT3042 voltage regulator (5.49 V). Additionally there is LT6655B 5 V voltage reference. Analogue part is essentially a DC circuit, the only really HF is internal 16 MHz master clock of the ADC.

Digital 3.3 V (mainly for powering of the digital interfaces) will be sourced from Raspberry PI. Thus, there will be 2 ground connection: external power supply and to digital interface of Raspberry Pi.

In this connection another question: referring to Figure 3, how do I make sure that return currents from the digital interfaces flow to the right ground connection (remember I have 2 of them)?

Additional concern: could the power distribution curcuit disturb sensitive measurements? I was going separate them by routing power on the bottom layer, but that is no longer a good idea in case of monolithic ground plane

And while I am still at asking: Assuming more or less monolithic ground plane on the bottom and signal/component layer on top, what is the best way to connect the negative side of bypass capacitors to the ground plane?

Answer

You got to think in terms of shared impedance (not resistance, really impedance).

Consider the parts of the circuit that use GND as a 0V reference for sensitive analog purposes. Obviously you want each of these "0V references" to be at the same "0V" potential. However current running through the GND plane will introduce an extra error voltage on top of each chip's "0V".

Now draw a schematic of your GND, with the currents running through it.

If you do not split the plane, but you have high currents running through it, because you put the power input connector on the left side, the power output connector on the right side, and the super sensitive analog bits in the middle, then you might have a problem due to high current flowing in GND and creating a voltage gradient.

Depending on frequency, consider impedance (ie, inductance, not just resistance).

Now, there are several solutions to this.

• You could put your power connectors in more reasonable places (ie, power input next to power output) so the high currents do not travel in your GND plane. This applies to all current loops which carry large, noisy, or high di/dt currents, like the internal loops of a DCDC, or the loops between it and its load (say, a cpu) or even the ground path between a decoupling cap and the chip it decouples.

Make sure you know where these loops are! Order them by troublesomeness (roughly "area * di/dt" for AC or "area*I" for DC). Placement is essential. A good placement with tight current loops makes layout much less of a headache.

• You could use differential amplifiers and ADCs which ignore common mode noise.

This is mandatory if the voltage to sense sits on a high-side current shunt. Now let's say you use a current sense amp for example. Dont forget whatever voltage is on its "output reference" pin (often mislabeled "GND") is directly added to the output... so dont stick the sense amp between two MOSFETs with its "GND" pin in the middle of the "motor current return" path...

• You could also split the plane, but then you need to decide where you gonna split it. And (this is where things get nasty) where you link your two grounds together at DC (or at high frequencies if you use isolators...

Let's name your two grounds AGND and PGND (analog and power). Some say to split, and join AGND/PGND or AGND/DGND under the ADC. This means any current that runs between AGND and PGND has to flow in the ground link under the ADC now, which is the worst possible place.

A solution that makes lots of sense is the "hidden split". Placement is essential. For example you put the power/noisy stuff on the right, and the sensitive stuff on the left. You place your decoupling caps so the supply currents loops running through GND are short and well placed. Then, since your board has two well defined zones, you can narrow down the width of ground plane connecting them, to ensure high currents do not run in the sensitive bits' ground.

It's very visual and difficult to explain, and placing your connectors properly is essential.

These tutorials are good: https://learnemc.com/emc-tutorials