How to read a text file using vhdl

I am working with altera QuartusII version 13.I want to write a program that reads data from a text file and outputs this data serially at every positive clk edge.

I have tried writing a code,but it did not work.The simulation result shows a value '1' for y(data read from) all the time even when reset is set '1' initially .Could someone help me in resolving this problem.

--code 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all; 

ENTITY readfile IS
port(rst,clk:in std_logic;
EOR:out std_logic;
y:out std_logic );
END readfile;


ARCHITECTURE behav OF readfile IS 
BEGIN
process (rst,clk) 
  file file_pointer : text;
    variable line_content : character;
  variable line_num : line;
    variable j : integer := 0;
    variable char : character:='0'; 
    variable cnt:integer range 0 to 80:=0;
begin

if rst='1'then
    EOR<='0';
    file_open(file_pointer,"C:\input.txt",READ_MODE);
elsif rising_edge(clk) then 
    if cnt<80 then
  readline (file_pointer,line_num);  
  READ (line_num,line_content);  

        EOR<='1';
        char := line_content;

        if(char = '0') then
            y <= '0';
        else
            y <= '1';
        end if; 
cnt:=cnt+1;
 end if;
end if;
  file_close(file_pointer);     
end process;

end behav; 

--text file(input.txt) 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0