mosfet - Ambiguous symbol

Does anybody know what this symbol presents?

Answer

Figure 1. Tri-state buffers with opposite control logic. Image source.

It's a combination or overlay of the two symbols in Figure 1. Rotate the symbol on the right by 180° and overlay on the symbol on the left.

Figure 2. Borrowing the symbol from KingDuken's answer but changing the infill to show the two buffers.

If the control signal is high the gate transmits from left to right. If the control signal is low the gate transmits from right to left.

Combining resistors in series with a voltage source in between

Am I allowed to combine the resistor R and coil Xl as if they were right next to each other? I want to make this into a current generator, without many transformations.

Answer

You can only combine two single elements into one for sake of analysis if they are in series with nothing else connected to the node between them, or if they are in parallel with nothing else connected in series between them.

So, do Xl and Z meet either of these criteria? If not, why not?

Can I wirelessly power mini LEDs?

I wanted to know if it would be physically possible to run LEDs off of some sort of transmitting device, wirelessly? It's important I be able to use extremely small LEDs and have the smallest possible parts connected to the LEDs to use them in the spaces I would like.

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I would like to be able to operate the LED up to a few feet away so it's not limited to being within just an inch or two of the transmitter.

The other thing I've noticed on some of the online videos is the coil that is connected to the LED is quite large. Ideally, I'm trying to get both the LED and whatever is necessary for the receiver component to fit within a 5mm W x 7mm H cylinder. Obviously, quite small.

Can this be done?

pcb - Solid ground-plane vs Hatched ground-plane

So recently when i was routing a PCB , I came across the option to either fill/pour my ground plane with either solid or hatched copper. I've also noticed that the old arduino duemilanove also had a hatched ground plane.

So what benefits does a hatched ground plane have over solid ground plane and vice versa.

Answer

As others said, it's mostly because it was easier to manufacture than solid layers for various reasons.

They also can be used in certain situations where you need controlled impedance on a very thin board. The traces width needed to get 'normal' impedances on such a thin board would be ridiculously narrow but the cross hatching changes the impedance characteristics on adjacent layers to allow wider traces for a given impedance.

If for some reason you need to do this, you can only route controlled impedance traces at 45 deg to the hatch pattern. This approach greatly increases mutual inductance between signals and consequently, cross-talk. Also note that this only works when the size of the hatch is much less than the length of the signal's rise time, this normally correlates to the frequency of the digital signals in question. As such, as frequency increases you reach a point where the hatch pattern would have to be so tightly spaced that you lose any benefit vs a solid plane.

In summary: Never use a cross hatched ground plane, unless you're stuck in some really weird situation. Modern PCB construction and assembly techniques no longer require it.

ul - What approval is required on custom made retail electronic items for sale in the USA

I have a custom built retail display unit + wall mount/table top unit, which I wish to sell to retail shops in the USA.

Retail display unit

1. It is powered by 24V DC, external power supply



2. Internally 24V DC is converted to 240V AC 50 Hz by inverter (Mean Well Inc.)


3. It has professional grade display screen powered by 240V AC 50 Hz


4. It has 24V DC to 5V DC SMPS (Mean Well Inc.)


5. Standard brought out SBC has HDMI port for display


6. Custom built interface board has low power RF 2.4 GHz network card for interfacing with "wall mount/table top unit"

Wall mount/table top unit

1. It's body built using acrylic sheet material


2. It is powered by 24V DC, external power supply



3. It has single/multiple 125 KHz RFID readers (custom built)


4. My custom SBC has serial port for RFID reader interface and low power RF 2.4 GHz network card for interfacing with "retail display unit"

What certifications are rrequired for both units?

Do I have to have a UL approval as well?

Isolated voltage and current measurement

I'm designing a safety shutoff circuit that monitors several power supplies, both voltage (12V, 24V, 72V) and current (up to 8A). These are entirely independent supplies, so I'd rather not tie the grounds together.

Measuring current of an isolated supply is easy with a hall effect sensor, so this is mostly solved. How would I go about measuring the voltage though?

I'm aiming at a solution that will always provide accurate measurements, even if the voltage is not in spec, so ideally the measurement would not depend on the measured voltage at all. While I expect the majority of cases to be either "no power" or "power good", I think that it is possible for a power supply to be connected in reverse, for the wrong supply to be connected (there are three different voltages in the system), the load to introduce back EMF or similar , so the circuit should tolerate a bit of abuse and ideally still provide valid data.

The simplest approach appears to be another hall effect sensor in line with a medium-sized resistor, but I fear that the large current nearby would disturb the measurement (especially as the measurement current would be fairly small compared). I can place the second sensor at right angles and attempt to get some distance to the other sensor, but I'm somewhat space constrained (20x20mm per channel, and there is also a zener diode and optocoupler here for quick "power good" sensing).

The application here is a CNC mill, which uses different voltages for different stepper motors, so different axes may fail independently. One of the motors has an electromagnetic brake, which should be engaged quickly when the motor's power supply fails, while the motor should not be moved when the brake cannot be released, and coordinated motions should not be attempted when an axis cannot be moved.

Answer

Simple voltage OK indication

Use a comparitor on each PSU to drive an opto-isolator if voltage is OK.

Analog voltage reading

Use a voltage to frequency circuit or voltage to pulse width circuit to drive the opto isolator.

Generating the PWM signals is easy using the LTC6992-1.

Figure 1. LTC6992-1 pinout and waveforms.

As can be seen, the configuration is simplicity itself. You need to use a potential divider to bring the expected voltage range down to 1 V max. Your pulse width will now be proportional to the voltage. Your receiver will need to measure the pulse width and the periodic time. The voltage can be calculated by the ratio of width to period.

^{simulate this circuit – Schematic created using CircuitLab}

Figure 2. Potential divider, PWM generator and opto-coupler.

---

In either case your controller can monitor the opto-transistor to deduce the status of each power rail.

speakers - Headphone wire color coding

How do I tell which wire is which if I have a copper wire, red and green coded wire? Is the unshielded copper wire ground?

Answer

Red is for Right. Blue (or green) is for Left. Copper is for ground (I remember this with the mnemonic Red Right bLue Left Copper Common). All 3 are coated in a lacquer you need to burn or scrape off before you solder. With standard headphone plugs, with the plug facing away from you, the right pin is right, the center pin is ground, and the left pin is left.

1. Common (or "ground")


2. Right


3. Left


4. Insulating ring

arduino - PWM an AC pump using MOSFET

I'm currently stuck on my project as I'm not sure what to do with PWMing my pump as I want to adjust the pressure.

I will be using an Arduino for PWM. The pump is 60W @ 230V 50Hz mains and is a vibratory pump, it has a built in diode so it only sees half of AC signal.

My question is would this circuit work? Do I need to add additional passive components? I think I do, but I don't know what or where should I add them.

Thanks in advance!

analog - Simplifying a circuit to measure current

So I'm to calculate the current in the places I put the ammeters in (yeah, I reckon one of them is turned around :)):

And while I can calculate such things for series or parallel circuits, I was taught I should first try to simplify the circuit and do it with Ohm's law and supplementary resistance. So I did something like that (which is my only idea):

And, regretfully, the results in the simulator are different. Then, how can I evaluate the 3 Ohm resistor (the one being "vertical" in the first picture) to somehow simplify the circuit and be able to calculate it? Could you please help? :)

Answer

Since this is homework, I'm not just going to give you the answer, but I will show you a method for attacking this problem. I'll use the same designators rawbrawb did. Whenever you show a schematic, add designators to make it easy to talk about. We don't want to be saying "the second from top resistor next to the switch" or something.

Immediately you should be able to see that this circuit has two parts, the mess of stuff formed by R1-R5, and R6. These two parts are in series. R6 is already as simple as it gets. You should be able to see that R1-R5 is equivalent to a single resistor from the rest of the circuit's point of view. Once you have the equivalent formed by the R1-R5 mess, you have two resistances in series and the solution should be trivial.

The problem now gets down to solving the equivalent resistance of the R1-R5 circuit. This you can break down into pieces. Pretend a 1 V source is applied to this circuit. If we can find the current drawn from that 1 V source, we can find the equivalent resistance by Ohm's law.

Start out by taking away R3. Now you just have two voltage dividers, R1-R4 and R2-R5. Each of these can be simplified into a Thevenin source. From inspection, you can see that the R1-R4 source is 1/2 V and 2 Ω. You can also see that the R2-R5 source is 2/3 V, and 2 seconds with a calculator tells you the resistance is 1.5 Ω. Now you can put R3 back between the two Thevenin sources:

At this point you should be able to solve for the voltages at each side of R3 easily. Once you have those, you go back to the R1-R5 circuit with 1 V applied and figure out the total current. From the total current, you can find the equivalent resistance. with the equivalent resistance of R1-R5, you go back to the original circuit and solve the total current.

eda - Import Gerber files into Altium

Question
I would like to import Gerber files into an Altium Designer PCB document for re-using an in-PCB spiral inductor but the importer fails to interpret the Gerber files in a correct way. Has anyone here knowledge on how to import Gerber files into an Altium Designer layout?

Background/What I have tried
The design containing this PCB spiral is a reference design from Linear Technologies and there are design files available for download here (clicking link will download a .zip-file). The design files contains a Mentor Pads PCB file but also Gerber files.

The ECAD system I'm using is Altium Designer 15.1. Since the Mentor PADS PCB file is of binary type I can't import it into an Altium Designer layout document. Altium designer can only import ASCII type Mentor PADS PCB files and I don't have access to conversion tools for converting from PADS binary format to PADS ASCII format. Therefore I tried to import the Gerber files into an Altium layout document. The result is not right at all, there is just a mess of top layer copper.

I have opened the Mentor PADS PCB file into the free Mentor PADS viewer and the design looks like it is supposed to. I have also imported the Gerber files into CAMtastic (the built in Gerber viewer in Altium Designer) and the design looks like it is supposed to. I also tried to export new Gerber files from CAMtastic and then import them into an Altium Designer PCB document but I had no luck with that.

Added to original post (1)
The way I've been trying to do the import of Gerber files into an Altium Designer PCB document is that I open a new PCB document and then I import one Gerber file at a time by choosing File->Import->Gerber File. I stop after the first import since I just get a mess of tracks and pads.

Added to original post (2)
Just opening the Gerber file using the Built in Altium CAMtastic viewer is not the complete answer for me. I would like to transfer some design elements from these Gerber files into a design for reuse.

Answer

I have downloaded the design you are dealing with. The gerber files, all layer files have .PHO extension.

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Import gerbers into Altium

If you rename the files as follows you will be able to open them in Altium:

• Layer4.pho \$ \longrightarrow \$ Layer4.GBL, this is the bottom layer


• Layer1.pho \$ \longrightarrow \$ Layer1.GTL, this is the top layer


• Layer2.pho \$ \longrightarrow \$ Layer2.GP1, GND plane 1


• Layer3.pho \$ \longrightarrow \$ Layer3.GP2, GND plane 2


• SoldermaskBottom.pho \$ \longrightarrow \$ SoldermaskBottom.GBS



• SoldermaskTop.pho \$ \longrightarrow \$ SoldermaskTop.GTS

I have identified the layers by the PDF appendix. For Pastemask (GBP, GBT) and Silkscreen layers you should search for their Altium extensions.

These modified files can be dragged and dropped into Altium, example for Top layer:

This way all layer files are easily openable in Altium.

---

Export TopLayer gerber into PCB document file

1. Select Layer1.GTL tab in Altium



2. 
   

   Select the Menu → Tables → Layers Order option. Following dialog will be shown: Fill the cells as below.

   
   

   

   
   


3. 
   

   Enable the Export to PCB option as follows: Menu → Tools → Netlist → Extract.

   
   

   
   

   "After a netlist has been extracted from your CAM data, the File » Export » Export to PCB command becomes enabled" source

   
   

   
   



4. 
   

   Now, select Menu → File → Export → Export to PCB and a new PCB document will be opened with the Top Layer.

   
   

   Result:

   
   

   

   
   

generator - Rated current of a three phase DG set

When the rated current of a 250 KVA DG set is shown as 347.8 A, does it mean that it is the line current or phase current or sum of currents on all phases say R Y B phases

operational amplifier - Use of 100K ohm resistor along with 0.1uF capacitor?

In the circuit diagram below, why is there a 100KΩ resistor (NOT R2) connected to the capacitor? To my understanding the capacitor-resistor act as a high pass filter to block the DC offset of the microphone, but since only the capacitor blocks DC why is the 100k resistor used? According to the author of the video (link below) he said, the 100k is used "not to overload the microphone's un-amplified output". I don't get this part.

Also, can only a capacitor be used in this circuit or any other circuit without the 100k resistor?

Passive RC high pass filter tutorial!

Answer

The resistor is there to provide a DC path for the input bias current of the opamp.

It is normally selected to be the same as the DC resistance connected to the other input, so that the bias current does not produce a voltage offset at the output of the opamp. But in this case, the effective DC resistance on the inverting input is only 1k||100k = 990Ω, so that benefit is not realized here.

It is also selected to be high enough that it doesn't affect the frequency response of the circuit overall (in conjunction with the DC blocking capacitor). In this case, 0.1 µF and 100 kΩ have a corner frequency of

$$\frac{1}{2\pi R C} = 15.9 Hz$$

This means that for frequencies above this value, the resistor will have no effect in the AC signal, but there will be a rolloff (loss of amplitude) below this frequency. This "loading" effect is probably what the author of the video was referring to.

transistors - Stability factors of a voltage divider bias circuit

I am trying to derive the stability factors of a voltage divider bias circuit. I could derive S,S', however, I'm facing some problem with the derivation of S''. Please help me in this regard.

How to find \$\frac{\partial I_C}{\partial \beta}\$?

The equations given in my book are these:

For a voltage divider circuit:

Kirchhoff's voltage law at the base circuit gives:

$$V_T=I_BR_T+V_{BE}+(I_B+I_C) R_E \tag1$$ $$I_B=\frac{V_T-V_{BE}-I_CR_E}{R_T+R_E} \tag2$$ The collector current \$ I_C \$ is given by: $$I_C=\beta I_B+(1+\beta)I_{CO} \tag3$$

Substituting \$ I_B \$ from 2nd eq to 3rd eq yields:

$$I_C=\beta\frac{V_T-V_{BE}-I_CR_E}{R_T+R_E}+(1+ \beta)I_{CO} \tag4$$

$$ I_C(1+\frac{\beta R_E}{R_T+R_E})=\frac{\beta(V_T-V_{BE})}{R_T+R_E}+(1+\beta)I_{CO} \tag {4a}$$

I understand and verified that the above equations came as a result of manipulating equations derived from Kirchhoff's voltage law and other current equations.

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In my book, they haven't derived the following equations(5,6,7), but have jotted down the equations as given below:

Then the stability factor can thus be expressed as: $$S=\frac{\partial I_C}{\partial I_{CO}}=\frac{1+\beta}{1+\frac{\beta R_E}{R_T+R_E}} \tag5$$

$$S'=\frac{\partial I_C}{\partial V_{BE}}=-\frac{\beta}{(1+\beta)R_E+R_T} \tag6$$

$$S''=\frac{\partial I_C}{\partial\beta}=\frac{1}{\beta(1+\beta)}[I_C\frac{(R_T+R_E)(1+\beta)-\beta SR_E}{R_T+R_E}+SI_{CO} \tag7 ]$$

I could derive equation eq 5 and 6 however I am facing the following issues with equation 7:

1) I am getting $$ \frac{\partial I_C}{\partial\beta}=\frac{1}{\beta(1+\beta)}[I_C\frac{(R_T+R_E)(1+\beta)-\beta SR_E}{R_T+R_E}-SI_{CO} $$ instead of $$\frac{\partial I_C}{\partial\beta}=\frac{1}{\beta(1+\beta)}[I_C\frac{(R_T+R_E)(1+\beta)+\beta SR_E}{R_T+R_E}+SI_{CO} $$

2) Why do we need to devive equation (7) ,in which stability factor \$S''\$ is in terms of other stability factors. Why wouldn't it be sufficient to say that \$ S'' \$ is given by eq 9a? or $$\frac{\partial I_C}{\partial \beta}=\frac{V_T-V_{BE}-I_CR_E}{(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})}+\frac{I_{CO}}{(1+\frac{\beta R_E}{R_T+R_E})}$$

3) How does eq 7 or 9a account for the fact that the Voltage divider circuit provides better stability against \$ \beta \$.?

4)If anyone has come across these equations, eq 5,6 and 7 in any standard book, then please mention the name of the book.

DERIVATION(MY ATTEMPT):

Partial differentiating eq 4a with respect to \$ \beta \$:

$$\frac{\partial I_C}{\partial \beta}(1+\frac{\beta R_E}{R_T+R_E})+I_C\frac{R_E}{R_T+R_E}=\frac{V_T-V_{BE}}{R_T+R_E}+I_{CO} \tag 8$$ $$\frac{\partial I_C}{\partial \beta}(1+\frac{\beta R_E}{R_T+R_E})=\frac{V_T-V_{BE}-I_CR_E}{R_T+R_E}+I_{CO} \tag 9$$

$$\frac{\partial I_C}{\partial \beta}=\frac{V_T-V_{BE}-I_CR_E}{(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})}+\frac{I_{CO}}{(1+\frac{\beta R_E}{R_T+R_E})}\frac{1+\beta}{1+\beta} \tag {9a}$$

From eq 4a:

$$ I_C=\frac{\beta(V_T-V_{BE}}{(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})}\frac{1+\beta}{1+\beta}+\frac{(1+\beta)I_{CO}}{(1+\frac{\beta R_E}{R_T+R_E})} \tag {10}$$

$$I_C=\frac{\beta(V_T-V_{BE})S}{(1+\beta)(R_T+R_E}+SI_{CO} \tag{11}$$ $$=> (V_T-V_{BE})=\frac{(1+\beta)(R_T+R_E)}{\beta S}(I_C-SI_{CO}) \tag{12}$$

Substituting eq 12 in eq 10

$$\frac{\partial I_C}{\partial\beta}=\frac{\frac{(1+\beta)(R_T+R_E)}{\beta S}(I_C-SI_{CO})-I_CR_E}{(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})}+\frac{S}{1+\beta} I_{CO} \tag{13}$$

$$ \frac{\partial I_C}{\partial \beta}=\frac{\frac{(1+\beta)(R_T+R_E)}{\beta S}I_C-I_CR_E}{(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})}+\frac{S}{1+\beta}I_{CO}-\frac{\frac{(1+\beta)(R_T+R_E)}{\beta S}SI_{CO}}{(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})} \tag{14}$$

$$=\frac{1+\beta}{1+\beta}\frac{(1+\beta)(R_T+R_E)I_C-\beta SR_EI_C}{\beta S(R_T+R_E)(1+\frac{\beta R_E}{R_T+R_E})}+\frac{S}{1+\beta}I_{CO}-\frac{S}{\beta}I_{CO} \tag{15}$$

$$=\frac{SI_C[(1+\beta)(R_T+R_E)-\beta SR_E}{\beta(1+\beta)S(R_T+R_E)}+SI_{CO}[\frac{\beta-1-\beta}{\beta(1+\beta)}] \tag{16}$$

$$\frac{\partial I_C}{\partial \beta}=\frac{I_C[(1+\beta)(R_T+R_E)-\beta SR_E}{\beta(1+\beta)(R_T+R_E)}-\frac{SI_{CO}}{\beta(1+\beta)} \tag{17}$$

$$\frac{\partial I_C}{\partial \beta}=\frac{1}{\beta(1+\beta)}[I_C\frac{(R_T+R_E)(1+\beta)-\beta SR_E}{R_T+R_E}-SI_{CO} ]\tag{18}$$

The sign of the last term should be +ve. Where might have I gone wrong?

operational amplifier - Current limiting with optocoupler

Update: I've removed all irrelevant information and simplified the question.

The OPA548 operational amplifier provides adjustable current limit that can be controlled digitally with a current-out DAC. Below is a circuit from the datasheet. I've calculated that Iset current 0~6.7µA will give me desired output range 0~100mA.

However, OPA548 is powered by isolated ±25V DC-DC. So, I would like to isolate current limit control too, using IL300 optocoupler.

Question Can I simply connect photodiode to control pin like this:

Or do I need something more complicated, like current mirror:

As I understand it, the first option corresponds to input range about 0.56 mA at forward gain K2 = 0.012. This is just a fraction of the optocoupler's normal operational range 10 mA.

I think the formula for resistors in second option is Ilim = Id * R1 / R2, which means it can be adjusted to better use operational range.

Answer

I think the best circuit for your purposes is the first one (o a slight modification of it I'll propose below): below I analyze the pros and cons of each one of them.

1. 
   
   

   Current mirror circuit: this circuits has many drawbacks and offers only one advantage. The main drawbacks are

   
   
   
   
   • 
     

     Increased current errors and temperature drift of the set current. The BJT current mirror invariably adds at least two errors:

     
     
     
     
     • \$V_{BE}\$ drift error: using a current mirror invariably implies the addition of a temperature drift to the reflected current \$I_{Lim}\$, due to its offset voltage temperature drift: $$ \frac{\mathrm{d}V_{os}}{\mathrm{dT}}=\frac{\mathrm{d}\left|V_{BE_{T_1}}-V_{BE_{T_2}}\right|}{\mathrm{dT}}\tag{1}\label{1} $$ This term, even if being small in many cases, is present: it implies a temperature depending variation of the difference between collector currents \$I_d\$ and \$I_{Lim}\$, even if \$V_{BE_{T_1}}=V_{BE_{T_2}}\$. It has to be minimized, therefore you cannot use two 2N3904 since their junction temperature could be very different rising the value of \eqref{1}: you should use a monolithic BJT matched pair like LM194, MAT01 etc. which are optimized from this (and many other) points of view.
     
     
     • Uncertainty in the reflected current \$I_{Lim}\$ due to low level transistor current gain \$\beta\$ limitations at low current level: basic circuit theory says that, for the standard current mirror as the one made of the \$T_1\$ and \$T_2\$ BJTs, the following formula for currents holds $$ I_d=I_{Lim}\left(1+\frac{2}{\beta}\right)\tag{2}\label{2} $$ This means that the difference between \$I_d\$ and \$I_{Lim}\$ is of the order of \$\beta/2\$. For currents of the mA order, \eqref{2} is not really a limitation: however, when your collector current drops below 10µA, you cannot use the 2N3904 as its current gain is not guaranteed at such low levels, and you can easily get \$\beta\approx 30\$. Again, you should use a monolithic BJT matched pair.
     
     
     
     
   
   
   • 
     
     

     Increased circuit cost: in order to minimize the problems caused by the circuit/physical problems expressed by \eqref{1} and \eqref{2}, you should use a monolithic BJT matched pair as already said. These devices can cost several Dollars/Euros, etc..

     
     
   
   
   
   

   The main advantage in using a BJT current mirror in this application is that, by using it, you can drive the OPAMP current programming pin with a circuit which is fully characterized from the electrical point of view, so you can reasonably predict its behavior by applying the ordinary circuit analysis techniques. The IL300 photodiodes are not througly characterized in their circuit behavior: for example their output resistance when used in current mode is not known.

   
   


2. 
   

   Direct photodiode driver circuit: this circuits has several advantages and offers only one drawback. Its main advantages are the following ones

   
   
   
   
   • Low drift of transfer current: this choice inherits all the IL300 drift/precision characteristics. Its excellent behavior under these aspects is mainly due to the fact that it is a negative feedback system.
   
   
   • Simplicity and economicity: it requires only the IL300.
   
   
   
   
   

   The main drawback of this circuit is that the IL300 is not fully characterized as an electronic component, as recalled in the description of the current mirror circuit above. However, this last problem can be solved by using a common gate JFET/MOSFET amplifier as shown in the picture below:

   
   

^{simulate this circuit – Schematic created using CircuitLab}

This circuit has all the advantages of the two solutions analyzed above, with the only minor drawbacks that it will cost a little more of the direct photodiode driver circuit. As a matter of fact, this circuit

• It is not influenced by gain variations of J1. The (low frequency) common gate current gain \$\alpha\$ for every field effect devices is practically 1, thus there is not any special requirement on J1. The only current ouput error is due to the \$I_{GS}\$ leakage current, which however is in the pA range: and if you choose a MOSFET instead of a JFET device (I used this one in the schematic since Circuit Lab does not offer the depletion mode MOSFET symbol), the behavior of the leakage current respect to temperature and voltage variations is even better.


• It is a negative feedback circuit. Temperature drift of J1 parameters are automatically compensated by the high source impedance, the D1 output impedance.



• It is fully characterized as an electronic circuit: the high impedance of D1 is loaded by the low source input impedance of J1. Then the output impedance at J1 drain can be estimated with reasonable precision, and this is true for all its other circuit characteristics.

Single quadrant analog multiplier

I wish to control a programmable power supply to deliver constant power (watts) into a heater. The heater resistance varies from unit to unit due to manufacturing tolerances.

• The PSU has a 'programmable' or remote setpoint input. 0 - 10 V gives zero to maximum voltage.


• The PSU has two feedback signals - one for output voltage and one for output current. These are 0 - 10 V signals scaled zero to maximum.

I'm wondering about the following approach to provide a solution.

^{simulate this circuit – Schematic created using CircuitLab}

• The analog multiplier MUL1 gives an output proportional to the product of the voltage and current.


• Op-amp OA1 compares the power level feedback with the power level setpoint (R3) and adjusts the voltage setpoint until the output power equals the setpoint.


• R1 and R2 set the gain of the response.


• C1 provides some filtering to reduce noise.

I only need a single quadrant multiplier as both feedback signals are positive. This raises the hope that I could find a single (positive) supply multiplier chip that with an output range of 0 - 10 V.

Q1: Are there any obvious problems with this approach?

Q2: I can't find a single-quadrant multiplier. (I've used the AD633 four-quadrant multipliers before.) Does anyone know of any?

Update 1

• The PSU voltage setpoint has an RC filter with protection zener on it. R is 1k and the time constant is about 1 - 2 ms so C is about 1 uF.


• The heater will be turned on for a second or so every five or six seconds.


• A power supply rise time to 95% voltage of 50 ms or so would be adequate.

mosfet - In an NMOS, does current flow from source to drain or vice-versa?

In an NMOS, does current flow from source to drain or vice-versa?

This Wikipedia page is confusing me: http://en.wikipedia.org/wiki/MOSFET

The above image confuses me. For the N-channel, it shows the diode's polarity going towards source in some, but away from the source in others.

I'm wondering which terminal should be connected to the power source (i.e. the positive battery terminal) and which should be connected to the power user (i.e. electric motor).

Answer

Conventional current flows from Drain to Source in an N Channel MOSFET.
The arrow shows body diode direction in a MOSFET with a parsitic diode between source and drain via the substrate. This diode is missing in silicon on saphire.

2a is a JFet so different topology.

2d is a MOSFET with no body diode. I've never seen one

\2e is a depletion mode FET - it is on with no gate voltage and takes negative voltage to turn the FET off. So diode has other polarity otherwise body diode would conduct whenever there was gate voltage.

three phase - Find impedence given per unit value-transformer

I really can't wrap my head around this. Three single phase transformers are connected to create a 3 phase transformer. They all have the same nominal values :

voltage conversion : 1.2kV/120 V (primary/secondary)

impedence: Z=0,05 pu

power: 7.2 kVA. They are connected in 4 different ways , star-star, star-delta, delta-star, delta-delta.

My problem is finding the actual value of the impedence when the primary side is connected in delta. I would normally find the base in the primary side like this : $$Z_b=\frac{V_b^2}{S}$$ where Vb is the primary side voltage and S the nominal apparent power value given.

Having a look at the solution manual though the base is supposed to be this $$Z_{b,old}=\frac{(V_b/\sqrt 3)^2}{S}$$

I've wasted too much time on this. Can somebody help? How can the connections matter since that 0.05 per unit value was assigned for the single phase transformers. Does a transformer's impedence change based on how it is connected?

How to calculate Tesla coil secondary inductance with spacing between the wire.

I have built a secondary coil for a tesla coil, and I used 24 gauge wire spaced with fishing line the same diameter as the wire.

I have found formulas for no spacing, but not encountered how to figure out inductance with spacing between the wire.

How can I calculate the inductance of the tesla coil if the secondary winding is spaced out instead of being right next to each other?

Answer

Lots of reference material for calculating inductance. Wheeler's formula link here works well. The length of the coil in the equation takes into account your spacing between turns.

How to use multiple LDR to trigger a led?

Whats the best way to use multiple LDRs to power up an LED? Currently I’m using one LDR which turns on an LED when it senses light. But now I want to use three LDRs (at different locations) to trigger the same LED. The LED should turn on when any of the three LDRs sense light. Thanks in advance!

sensor - Method required to enable a toy "vehicle" to follow a "target" wirelessly?

I am trying to create a small robot toy car with the ability to follow a person around, with a range of about 50 m.

Ideally the person will be provided with a small transmitter of some kind, and the car will have a receiver which will allow it to determine the direction to the transmitter so that the car can follow the person holding it.

However, I understand that systems such as infrared require line of sight to operate, while others like WiFi are too omnidirectional to pinpoint the transmitter direction.

Is there any recommended method or system that would meet my requirement?

---

Added:

Notes:

To elaborate, it is more for remote photo taking.
A person would hold a remote tag and trigger a command; after which the robot would seek out the person, and position itself in the same direction to take a shot.

Unfortunately GPS not not a solution as for this application is mostly for indoors. I understand RFID tags may work although i am not sure if it has sufficient directionality

Buck converter operation

I have been reading about the buck converter and have also referred to the various online resources like here.

In the above circuit, as I understand, when the switch closes, current starts to increase across the inductor linearly with time. What is the voltage at the output?

Current increasing would mean that the current across resistor would also increase linearly, and hence the voltage should practically be increasing, and not be stable, so how does it become stable/constant?

What exactly happens when the switch is opened?

The capacitor would cause ripples to pass through, but what about the resistor? From what I understood, the current decreases linearly with time and is due to the inductor (energy stored previously). But since it's decreasing, wouldn't the voltage at the output also decrease linearly with it?

So how do we get a stable output?

I guess the timing /duty cycle of switch would play a major part, but I still couldn't figure that out.

Answer

Here's the picture: -

It's significantly more complex than what I'm going to say but bear with me: -

Firstly I'm going to ask you to imagine that D1 is a switch like SW1 but, it closes when SW1 opens. What you then get at point (2) on the circuit is a square wave; it has a peak of Vin (let's say 10V) and rapidly drops to 0V when SW1 opens (remember I've asked you to consider that D1 is also a switch). This repeats at some arbitrarily high frequency such as 100kHz.

Let's also say that Vd (your output) is desired to be 5V. Now if the 10V squarewave at (2) spent half of its time at 10V and half of its time at 0V then the average value would be 5V i.e. exactly what you want.

Should you in fact require Vd to be 3.3V then the squarewave at (2) would spend about a third of its time at 10V and about two-thirds of its time at 0V. (Remember I'm asking you to consider that D1 is a switch that closes when SW1 opens).

So you've got a squarewave at (2) that has a duty cycle of (say one-third) AND now you have a low pass filter formed by L1 and C1 - the output from this is pretty much a dc voltage at 3.3V.

Then, you put a load resistor on (\$R_L\$) - does this alter the output voltage average level? The answer is virtually "no" because you are using an inductor and capacitor to form a low pass circuit and providing the inductor's internal resistance isn't too big then there won't be too much of a dc voltdrop across L1 and you'll still get 3.3V at the output.

However, if you load the output too much, the 3.3V will start to droop and this is when the control circuit starts to take over and apply a little more than one-third duty cycle to SW1 being on. This control loop is fundamental in all buck regulator circuits but it isn't necessary to understand the ins and outs of this to comprehend the basic working.

So far I've assumed D1 is a switch (like SW1) and what 've described is called a synchronous buck regulator - it uses two MOSFETs; one for SW1 and one in place of D1. I think it's easier to approach synchronous buck regulators first then move on to understanding standard (but less efficient) buck regulators.

Standard buck regulators have D1 (not a switch) and they would like D1 to behave like a switch (as described above) but it doesn't always do this. For a start it drops 0.7V across it when it is acting like a switch (maybe a bit less if you use a schottky diode). It conducts like a switch but the 0.7V across it loses energy in the form of heat - it can never match the efficiency of the synchronous regulator.

How does D1 behave like a switch - when SW1 is closed, a ramping current runs through L1 and when SW1 eventually opens, the back emf from L1 drives (2) negative in order to keep the current through L1 still flowing. This is the nature of inductors and if this is a little alien to you go and study inductors. This negative voltage rapidly falls below 0V until D1 starts to conduct - now it is behaving like a synchronous regulator (albeit with 0.7V drop across it). SW1 eventually starts conducting again and the cycle repeats.

Previously the squarewave described at point (2) was 10V peak and 0V at the bottom - now it is 10V peak but -0.7V at the bottom. L1 and C1 are still a low pass filter (as mentioned previously and if the duty cycle of the square wave was one-third, the voltage at the output would be about 3.1V. The control system would take over and alter the duty cycle until the output was 3.3V.

But there's a further problem when D1 is just a diode (and not a switch) and this really does make non-synchronous buck regulators quite tricky to get to grips with. If the load is very light, D1 doesn't act like a switch (as per a synchronous regulator) and the output voltage rises and rises because the energy stored in L1 keeps getting pumped into C1 and of course the output voltage rises. It's not a big problem because the control loop keeps this in check by applying ever smaller duty cycles the the squarewave at point (2).

I've got the point in my explanation where I need to take a break so if you manage to wade through this and want more let me know. The upshot of what I would explain is surrounds storing energy in the inductor (when SW1 closes), transferring it to the capacitor and making sure that the transferred energy \$\times\$ frequency (cycles per second) matches the power needed by the load resistor at the voltage the regulator is intending to regulate at.

Synchronous regulators are far easier to explain!!

signal - Which one is better as voltage divider: resistive, capacitive , low pass filter,...?

There are different types of voltage attenuators for AC signals ( a short explanation is here). The most well known is a resistive one. Others like capacitive, inductive or low pass filters are available ( Low passes may include many designs including passive or active .Thanks to Andy Aka who provided a very good link to them in another thread). I know asking which one is better (especially for high frequencies) is not a good question and the answer is :"It depends".

What I want to know is their advantages and disadvantages of them that may lead to a conclusion for selecting the best design.

Answer

There are basically two types of attenuator I would consider and these can be combined in a couple of ways: -

• (A) is used because it offers simplicity with the ability to design it to suit the driving source and what it interfaces to (centre tap).


• (B) is used when you want to "ratio" down an AC voltage whilst not being concerned with the DC levels but for it to work reasonably at low frequencies the capacitances need larger values than for RF signals.


• (C) is a combo of A and B and gives you a broad frequency range of constant attenuation from DC to RF


• (D) I used once for monitoring the output of a high voltage dc power supply - the main top element of the resistive part of the divider was tens of Mohms and due to its size and proximity to high voltage switching circuits picked-up a lot of noise. Adding caps in the same impedance ratio as the resistors was a beginning but the potential for high currents through the capacitors was a worry so resistors were added in series. Because the voltage divider was used as part of a feedback element controlling the high voltage I had to make sure that what was measured was translated accurately else instabilities might occur and at 50kV it didn't need much instability to destroy circuits. The extra resistors in series with each cap also served to limit currents into the op-amp that the "centre-tap" connected to.

This is just a snap-shot of probably many more techniques.

capacitor - Dealing with Motor Noise

Generally 0.1 μF 50 V ceramic capacitors are connected across the motor terminals to reduce noise. How this value is decided? Does it depend on the motor rating?

LED light bulbs flicker when switched off - where does the energy come from?

Outside my house, at the front, I have a set-up of 3 lights attached to the wall. These lights can be switched on using a switch inside the house. Furtermore, they are attached to an infra-red sensor which can switch the lights on for 2 minutes at night time, when someone passes by. I have this same set-up at the back of my house. So far, so good.

I recently changed the light bulbs from incandescent to LED. At the back of my house, this worked fine. The set-up at the front of my house resulted in the LED lights flickering when switched off. If I place back 1 incandescent light bulb, leaving the other two lights LED, this problem does not occur. Following the post Mains LED light bulb flickers when switched off, I understand how LED lights work and why they can flicker. My remaining questions are:

• Where does the energy come from leading to the flickering?


• Can I change something in the switch or the sensor to make it stop?



• Why does the addition of an incandescent light bulb stop the LED lights from flickering?


• Is a set-up with all incandescent light bulbs using up the same amount of energy, without me noticing as easily?

Answer

Apart from what Brian says, which may very valid in some cases, there are also other options for why this happens:

1. The IR sensor hasn't got a relay but solid state switches: Solid state switches can always leak a tiny amount of current. This is why solid-state switch or dim packs in lighting rigs for shows need to be un-powered before people are allowed to modify cabling, as the leakage a "turned off" >10A triac can give, especially when aged a little can be dangerous or lethal in some cases. Depending on the design and Q.A. of the IR sensor the difference in leakage between one and another can be quite large.


2. The sensor showing the problem has more contamination/dirt on the inside, due to wind or rain or even due to sunshine degrading the plastic joints letting water and dirt in over time. This then creates creeping current between the switch contacts.


3. The IR sensor has a snubbering circuit that creates a leakage capacitance across contacts, which acts the same as the wire capacitance Brian mentions: A capacitor at AC (changing current directions) becomes a sort of resistance to the current flow, and thus allows a little leakage current through.


4. One of the switches in the system has a NEON pilot light, either hidden or still visible, which leaks a few mA of current through the load lamp.

A pilot light is connected like this, for reference:

^{simulate this circuit – Schematic created using CircuitLab}

With an incandescent lamp, when the switch is open, you can see that the 250 Ohm of the lamp does not add much to the 30kOhm already in the loop, so the neon light will turn on, and only 1 to 2mA will go through your ceiling light, which will not turn it on at all, won't even get warm, as across the 250 Ohm it presents 2mA is only 0.5V, way too little for a 115V lamp to turn on.

Now a leaking Triac will also be in the range of 2mA to 10mA, so will most capacitive coupling. Creep (before other paths will trigger earth faults that should cause a power shut off) usually stays under 50mA. All of those current are much too low to cause any noticeable effect in the wire of the incandescent.

But what happens when that current goes through a LED bulb? Well, a modern CFL or LED bulb usually has very low, to nearly zero internal leakage, so then the internal circuitry can be seen as this (they are much more complicated if well designed, but for this purpose, this is the representation):

^{simulate this circuit}

When you have a hard switch, all is well, switch on: Light on. Switch off, light off.

Now, what happens if you have something "pumping 5mA" into the lamp continuously? 5mA is still not enough to power the LED, right, so... That should not turn it on at all, 5mA is only 500mW, and your LED bulb is, let's say 10W, so the maths is clear.

Well, because there is no leakage, the 5mA will just charge the capacitor. If we assume the current to be perfectly constant (not entirely true, but close enough), it will charge up over time like this:

dV = (dt * I) / C with C = capacity of the capacitor, I is the constant current, and dt is the time period, and dV is the change in voltage.

At some point the capacitor charges to the turn-on voltage of the controller, and the LED will turn on, using the energy in the capacitor. Because your bulb drains the energy in the capacitor much quicker than the current can replenish it it will drop to the turn-off voltage and turn off.

Depending on the size of the capacitor and the turn-on and turn-off voltages of the controller, the flickering can be quick, slow, or even so quick that it looks like an always-on bulb that flickers in brightness.

These flickering speeds also get influenced by the number of bulbs connected.

Funny thing is, that based on the flickering pattern of 3 or more lamps connected to one system it is possible to make some assumptions about what might be the cause. While no guarantee, it has some basis in analysis that is valid.

If they all flicker in an nearly synchronous pattern, the leakage current is highly voltage dependant, whereas if they flicker less in sync the leakage current is more constant, and this may give hints about where to seek when there is a full scope of the entire system.

As a side note: If the flickering is a real "fluid" flickering in an on-state it may be that the LED controller leaks the current through into the LEDs without actually turning on and the flickering is caused by much smaller on/off margins and inferring anything from a pattern is much harder.

---

Will this energy also leak away if there are incandescents? Yes! As I showed you above, the current flows, you just don't see it. So in a way with the LED lights you're already winning, if you can get past the flicker annoyance, because now at least the leakage is doing something for you.

The reason the flickering stops when you add only one incandescent is basically also already answered: If you add the low-resistance lamp in the loop, the leakage will only cause up to a few volts maximum on the wires, which is way too little for the High-Voltage LED driver to turn on, or to leak into the LEDs themselves.

batteries - AA Battery capacity

The load is 227mA at 25ms (this is pulled 20times in a minute )and 0.001A for the rest of the time from 4 AA batteries. If this test is running for 20 days, I need to calculate the voltage left on the battery after 18 days.

http://www.toshiba-batteries-eu.com/sites/default/files/imagesfiles/Standard_Alkaline.pdf

My calculations for battery capacity are as follows

227mA *25mS + 1mA *2975mS = 8.65mA Typical AA Battery life is 2000mAH Battery hours 2000/8.65= 231hours 20 days is 480 hours 480/231% of battery consumed in 20days? is this right or am I looking at this incorrectly.

How are DACs integrated in color LCD screens?

I'm having trouble imagining what actually happens inside an LCD screen.

I picture digital RGB data for each pixel getting sent to the screen through a connector. Lets say we have 24-bit color for each pixel, so 8 bits each for red, green, and blue subpixel. Inside the LCD, for each subpixel a voltage must be applied to control its intensity. This is where a DAC must come in to convert each 8 bit intensity value (digital) to a proportional voltage (analog). But, surely there is no DAC for every subpixel? My laptop screen is 1920x1080 so it has over 6 million subpixels.

So, how are these DACs integrated into the architecture of this LCD? How many DACs are in a single LCD screen?

I read that a transistor is used to select a particular liquid crystal cell and charge it/light it up, and a capacitor holds the charge briefly until the next refresh cycle. So that would eliminate the need for 6 million DACs, although it would mean you need 6 million transistors and capacitors. But I'm still wondering about these DACs - they never seem to get mentioned because people consider LCD screens "digital".

digital logic - Rewriting a boolean expression only using NAND

So I had a truth table and using a Karnaugh map I simplified a function. I obtained.

\$ f = \overline{A_3}A_2\overline{A_1} + \overline{A_2}\overline{A_0} + A_3\overline{A_0} \$

Then using the distributive property of boolean algebra:

\$ f = \overline{A_3}A_2\overline{A_1} + \overline{A_0} (\overline{A_2} + A_3) \$

Ok, with this we have the minimum of logic gates to use.

Now I need to convert this to NAND. What seemed easier to me was to take the logigram (or electrical scheme) and directly change the gates to their equivalents with NAND. I obtained:

\$ f = \overline { \overline{\overline{A_3}A_2\overline{A_1}} \cdot \overline{\overline{A_0} \overline{A_2 \overline{A_3}}} }\$

Now I have two questions about this:

• 
  

  How should I proceed algebraically to pass to one expression to another (I know I need to apply DeMorgan laws or use the complement of the function... I would thank if someone can give like a tip or something on how to start doing it.

  
  


• 
  

  I'm thinking if there is any way to simplify the NAND expression... I see that I have \$ A_2 \$ twice and also \$ \overline{A_3} \$ twice... I'm thinking if there is any way to go even further in the simplification... If someone could also give a tip on how to proceed to not ruin the rule of using NAND only. Thanks very much!

  
  

Can all USB Type-C to Type-C cables themselves handle 100 W?

I am designing a machine and trying to make it look aesthetically pleasing.

Could I use off the shelf USB Type-C to Type-C cables to handle both power deliver and encoder data to/from a motor?

The DC motor is about 80W (@24 V) and uses 2 leads for power and 8 for the encoder. Could I technically use just one USB type cable to achieve this? I would not use the type-c connector, just the cable. The encoder has differential wires so hoping interference would not be an issue.

I understand that passive type-c cables are rated for only 3A but is that limitation due to the cable or the connectors and electronics in them?

Answer

Can all USB Type-C to Type-C cables themselves handle 100 W?

That's really not the right question since the power (hopefully) isn't consumed in the cable. When choosing a cable you need to be mindful of:

• Current carrying capacity. This is affected by wire material (Al, Cu, etc.), cross-sectional area and its ability to dissipate heat in the working environment (free-air, conduit, etc.) without melting the insulation.


• Voltage rating. How many volts can the insulation withstand between cores and between cores and ground.


• High frequency requirements. This is beyond the scope of this answer but includes EMI, cross-talk, shielding, etc.



• Acceptable voltage drop. Voltage drop will be proportional to the product of length and current. To meet the maximum allowed voltage drop requirements the cross-section area of the wire may have to be increased.

So a better question would be:

Can all USB Type-C to Type-C cables handle 3.5 A at 24 V.

---

Figure 1. Hybrid power and data cables for servo applications. Source: MacRAE'S BLUE BOOK.

Depending on the size of your project it may be worth searching out suitable quantities of hybrid servo cable. Lapp, for example, do a wide variety but you may have difficulty buying in small quantities.

power - Is it ok to feed the output of one LDO regulator to the input of another?

Sorry if this is a stupid question, but I am mainly working with 5V PIC circuits and now want to integrate a component (nRF24l01+) that needs a 3.3V supply.

As I have a box full of ~7V wall-warts, I normally use a 7805 or similar LDO regulator to power the circuit. Now I want to also get 3.3V without using a separate external supply.

I'm looking for guidance on the "right" way to do this. I think the options are:

1. Use a voltage divider on the output of my 5V regulator to get 3.3V


2. Use a 3.3V LDO regulator fed directly from the 7V wall-wart


3. Use the output of the 5V regulator as input to a 3.3V regulator

I can see that all of these would work (would they?) and that option 3 seems to waste least power, but I don't know what gotchas might arise by chaining two regulators like this.

What things do I need to consider when making this choice?

Answer

1. 
   

   Do not use a voltage divider circuit to power something like an RF transmitter, that will not work during pulsed currents as the "load" equivalent resistance drops when it needs more current, and therefore the divider will not actually "Regulate" at all.

   
   


2. 
   

   You can do this, if you do not trust your 7805's other parallel loads, and this will probably help protect the 5V system from noise feedback from the RF system, which you may get in the #3 option. In this method, make sure both regulators have good input capacitance, and also reasonable output capacitance (follow datasheet recommendations, usually put a little extra to avoid spike brownouts which often happen, especially with RF modules).

   
   


3. 
   

   yes, I would put the LDO after the 5V 7805's output, as long as the dropout is actually within spec. Go for one with less than 1V drop out and you should be fine. Ensure plenty of capacitance between the two regulators, and on the LDO's output stage to feed the pulsed TX currents of the NRF24.

   
   
   

These 7V wall warts I assume have enough output current to run your system. You just mention some 5V PIC-based circuits, which I assume are low-powered. The NRF24 is low power, but has high power bursts which can brown-out and cause things to reset (just see all the other questions on EE Stack Exchange about power issues with RF TX/RX modules hehe). To fix this, always ensure good and fast acting capacitors are available nearby, and are properly rated.

Capacitor chemistries like tantalum and ceramics are the fastest to respond to pulse currents, and have the least ESR (equivalent series resistance, this is effectively what slows down other capacitor types). A cheapo electrolytic capacitor has very high capacitance but often poor ESR characteristics, making them slow to react and therefore their "reactance" at high frequency (fast pulsed loads) means they are almost useless.

Your 3.3V system should be okay from either the 7V wall wart output or the 5V 7805 output, but like I said check the dropout, check the rating of the 3.3V LDO (some have ~6V max voltage ratings, obviously you cannot use the 7V input in this case). Also make sure current ratings for all regulators in your system can handle their respective loads, and if the 7805 is near to it's max load already it's best not to attach the LDO to it.

EDIT: I actually cover some basic things exactly like this, in a 'Seminar' thing I made for my uni's robotics club. Check it out here, in PDF format

operational amplifier - Transfer function of a summing integrator

I'm trying to derive the transfer function of a summing integrator for use in a feedback circuit. The single input and double input integrators are shown below.

An integrator with one input is derived such that:

$$V_{\text{OUT}} = -\frac{1}{RC}\int V_{\text{IN}}dt$$

For gain in the frequency domain, this becomes:

$$\left\lvert\frac{V_{\text{OUT}}}{V_{\text{IN}}}\right\rvert = \frac{1}{\omega R C}$$

So because at the negative terminal of the opamp, these input voltages are summed, the summing integrator transfer function is:

$$V_{\text{OUT}} = -\frac{1}{R_{\text{fb}}C}\int V_{\text{fb}}dt - \frac{1}{R_1C}\int V_{\text{IN}}dt$$

My question is, in the frequency domain, does this simply become:

$$\left\lvert\frac{V_{\text{OUT}}}{V_{\text{I}}}\right\rvert = \frac{1}{\omega R_{\text{FB}} C} + \frac{1}{\omega R_{\text{IN}} C}$$

Where \$V_{\text{I}} = V_{\text{FB}} + V_{\text{IN}}\$ and the output is 180 degrees shifted (90 degrees + 90 degrees).

Answer

No, the last step of your analysis is not correct.

Remember, as long as the opamp output does not saturate, the feedback through the capacitor keeps the inverting input at ground potential, the same voltage that's at the noninverting input.

Therefore, \$R_{\text{1}}\$ and \$R_{\text{FB}}\$ are converting \$V_{\text{IN}}\$ and \$V_{\text{FB}}\$ into currents, and it is the total of these two currents that gets integrated in \$C\$, producing the output voltage.

With a bit of hand-waving (keeping in mind that voltages and currents become phasors, which means that the phase relationship between \$V_{\text{IN}}\$ and \$V_{\text{FB}}\$ at the frequency \$\omega\$ affects the result), you could say that

$$ V_{\text{OUT}} = \frac{V_{\text{FB}}}{\omega R_{\text{FB}} C} + \frac{V_{\text{IN}}}{\omega R_{\text{IN}} C}$$

But it should be obvious that you can't define \$V_{\text{I}} = V_{\text{FB}} + V_{\text{IN}}\$ and get your final equation from this.

The gain with respect to each input is NOT affected by the other input resistor(s) — however many there might be.

---

Actually, when you get right down to it, your second equation is incorrect, too.

When you convert to the frequency domain, the full equation is

$$V_{OUT} = \frac{1}{j\omega R_1 C} V_{IN}$$

and if you want to ignore phase angles and just talk about magnitudes, you can write

$$\left\lvert V_{OUT}\right\lvert = \frac{1}{\omega R_1 C} \left\lvert V_{IN}\right\lvert$$

or

$$\frac{\left\lvert V_{OUT}\right\lvert}{\left\lvert V_{IN}\right\lvert} = \frac{1}{\omega R_1 C}$$

which is NOT equivalent to what you wrote. In general, for complex numbers \$X\$ and \$Y\$, \$\frac{|X|}{|Y|} \neq |\frac{X}{Y}|\$

transistors - Silicon Controlled Switches: applications&suppliers

I came across this description of what are called "silicon controlled switches." I always look to balance n/p-channel electronics for stability, and using these silicon controlled switches seemed like the perfect way to do so. However suppliers seem few and far between, and the few products I could find were >=$50 a piece!

I could find very little information on these devices online, so I am wondering what technological niche they fill, and if anyone sells them at a reasonable price--i.e. on the order of the price of the components an equivalent circuit made out of regular transistors. If not, why are they so expensive?

I am beginning to suspect that they are more commonly known/sold under a different name.

Answer

An SCS is a specialist device that is now seldom available. The equivalent circuit is shown in the page that Feynman referenced. It's main claim to fame is that it is a TRIAC like device that can be driven off in the middle of a conduction cycle using gate drive alone, unlike a TRIAC.

• 
  

  A TRIAC or SCR can be driven off mid conduction by interposing an inductive reverse conduction inducing current spike, but that is unusual* and cheating, as conduction is stopped by stopping conduction.

  
  


• 
  

  A number of high power camera flashes use this method to terminate flash cycles.

  
  

You can buy an SCS here for $US17.50/25. Given that it is a 1400 Volt x 112 Amp device the price is "not bad". Datasheet here.

An SCS (Silicon Controlled Switch) is a device whose time has largely passed. It lingers on in very high voltage high current niche applications but would almost certainly not be used for new work.

An equivalent functionality can be provided by using 2 x MOSFETS (2 x P or 2 x N channel) connected in series with sources connected and gates connected (!!!).

You thus get a module where the current path is

---[DS]-[SD]--

Driving the 2 connected gates +ve relative to the two connected sources (for an N channel pair) turns the pair on and connecting the two connected gates to the two connected sources turns the pair off. this then is a true bilateral (bidirectional, 4 quadrant) swith - about the most flexible switching device available. Even better than an SCS if you can but an SCS :-).

To equal the above SCS you could use two of something like the IXYS MOSFET (same brand as the SCS) IXTY06N120P 1200V 90A MOSFET priced at $2.79/25 at Digikey but not in stock. It's a TO252 package which is capable but which may get "somewhat stretched" [tm] at those power levels.

In most cases a more normal topology MOSFET or TRIAC solution will do whatever job you have well enough.
There is little that you cannot do with an H-Bridge :-).

http://search.digikey.com/us/en/products/IXTY06N120P/IXTY06N120P-ND/2117410

vhdl - Syncing Signals with Global Clocks in FPGAs/CPLDs and Edge Detection

I am a newbie in digital logic design and I'm trying to get my head around syncing external signals to the global clock in an FPGA. For example, the SCK signal/clock fed to an FPGA by the SPI Master. I understand this can be done as follows in VHDL (code taken from http://www.doulos.com/)

entity SyncClocks is
port( SCK   :   in std_logic;
        CLK :   in  std_logic;
        rise    :   out std_logic;
        fall    :   out std_logic);
end SyncClocks;

architecture RTL of SyncClocks is

begin
    sync1: process(CLK)
        variable resync : std_logic_vector(1 to 3);
            begin
                if rising_edge(CLK) then
                    rise <= resync(2) and not resync(3);
                    fall <= resync(3) and not resync(2);
                    resync := SCK & resync(1 to 2);
                end if;
            end process;

end architecture;

Simulating the above results in:

Now I know why the Rise/Fall signals are delayed by two clocks - it's because SCK goes through two flip-flops. I've also been told that it's better to act on these rise and fall signals than on the SCK signal itself. My question is doesn't this two-clock delay actually affect how the data is transferred? Let's suppose I have a microcontroller acting as SPI Master and talking to my FPGA, which is a SPI Slave. They are operating in SPI Mode 0. Furthermore, let's assume the FPGA needs to transfer some data to the microcontroller.

As soon as SS goes low the microcontroller will expect a bit to be present on the MISO line which it will sample on the rising edge of SCK. When SCK falls the FPGA has to shift out another bit onto the MISO line - but the FPGA waits two clock cycles because of our sync. and edge detection. In other words, it won't actually shift out on the falling edge of SCK it will shift out when the signal "Fall" is '1' in the above example.

Will this not cause problems on the microcontroller end? Obviously the microcontroller has no knowledge of Rise/Fall and it's clock may be running completely independently at a different frequency.

I have been trying to think this through and it seems to me that the problem will not occur if the SCK signal is slow compared to the global clock. This is because even though there is a delay it doesn't matter because the FPGA will shift out a bit 'quick enough' anyway i.e. before SCK rises. How wrong am I?

Answer

Your FPGA design is using the fall signal to clock out data on MISO. But its probably using rise to clock data in from MOSI. The microcontroller will do the same thing. It knows the falling edge of SCLK is telling the slave to change the MISO line, so it won't clock that data in until the rising edge of SCLK. You have to be sure that your FPGA clock is fast enough that even with two clocks delay on detecting the falling edge, it will be presenting valid data to the microcontroller by the time of the rising edge.

This arrangement not only gives your slave device some leeway in how quickly it responds to SCLK, it also allows for some uncertainty about whether the SCLK or the MISO traces or cables are the same length. By sampling MISO in the middle of its valid period, you allow the SCLK transmission delay to be either longer or shorter than the MISO transmission delay. Another way to say this is that the SPI receiver is designed with balanced set-up and hold times.

This is different from the way you normally arrange data transfer between gates in your FPGA. There, your flip-flops generally have zero hold time. That is, they clock old data in on the same edge when the upstream flip-flop is changing its output state. They can do this by delaying their data inputs just a little bit more than their clock inputs, and its an arrangement that generally gives the best possible maximum clock rates while still being relatively easy to guarantee the timing with automated tools.

The balanced set-up and hold arrangement on SPI can't achieve the same high clock rates as the interfaces within the FPGA, but it also doesn't require anywhere near as careful management of the propagation delays between the sender and receiver.

555 Monostable Timer delay

I have built numerous 555 circuits over the years. I recently had to built a Monostable 555 cct. as per this site : http://www.allaboutcircuits.com/vol_6/chpt_8/4.html

The cct. is used in a motor vehicle. When the remote control is pushed to open the doors, it sends positive 12V to this Monostable cct. to initiate it and a 3 Amp Power Transistor pulses the siren momentarily to indicatse "unlocking" by audible means.

The issue I have is that Rt and Ct used to time the output pulse is not short enough. I replaced these components to the smallest values I could get, but the output is still "too long". Teh siren makes a "chooow" sound instead of "chow". Sounmds too unprofessional or after-market.

Any ideas to get a short pulse (nearly a few micro seconds) out of this old 555 cct. ?

capacitor - What do you call it when you add energy to an inductor?

When you add energy to a capacitor, you say that you are "charging it". (This is kind of a misnomer, since the total amount of charge in the capacitor is the same, but whatever.)

But what do you call it when you put current through an inductor, and it ________es up and forms a magnetic field?

Edit: Actually, using "charge" for a capacitor is not a misnomer, as shown below and in 'charge' etymology, though it leads to confusion, with people mistakenly thinking that capacitors store electric charge, when in actuality, the charge of energy just moves the electric charge from one plate to the other.

Answer

The word is simply energizing. It is actually used quite often when referring to superconducting magnets, which are nothing but inductors. http://en.wikipedia.org/wiki/Superconducting_magnet#Persistent_mode

operational amplifier - OP Amp with T network feedback

Hello i want to know how to calculate the equivalent T network resistors in the inverting amplifier below (the answer is 10M but i dont know how) ,i dont need formula but indepth circuit analysis ,thanks

Answer

Your writing isn't entirely clear. But since you gave the answer you seek, I think I understand what you meant. You want to know how the output affects current entering the inverting input by way of the T-network. Your goal is to find the equivalent \$R_F\$ (if I do understand you) that would have a similar result as in:

^{simulate this circuit – Schematic created using CircuitLab}

(Above, I've treated two resistors as being the same value, \$R_T\$, to help simplify things a little bit.)

Given that the inverting input can be taken as close to \$0\:\textrm{V}\$, for the purposes here, the question is essentially just asking, "How does voltage at the amplifier output affect current entering the inverting node?"

To figure that out, first figure out \$V_X\$:

$$\begin{align*} V_X &= \frac{V_O\cdot R_G\cdot R_T+0\:\textrm{V}\cdot R_T\cdot R_T+0\:\textrm{V}\cdot R_G\cdot R_T}{R_T\cdot R_T+R_T\cdot R_G+R_T\cdot R_G}\\\\ &= V_O\frac{R_G}{R_T+ 2\cdot R_G} \end{align*}$$

From that, you can easily compute:

$$\begin{align*} I_X &=\frac{V_X}{R_T}=\frac{V_O}{R_T}\frac{R_G}{R_T+ 2\cdot R_G}\\\\ &=\frac{V_O}{\frac{R_T\cdot\left(R_T+ 2\cdot R_G\right)}{R_G}}\\\\ \therefore R_F &=\frac{R_T\cdot\left(R_T+ 2\cdot R_G\right)}{R_G}\\\\ &=R_T\cdot\left(2+\frac{R_T}{R_G}\right) \end{align*}$$

The result is \$R_F\approx 10.004\:\textrm{M}\Omega\$

---

Just a note about T-networks, from my own personal experience with electrometers. (I was experimenting with circuits achieving below \$1\:\frac{\textrm{fA}}{\sqrt{\textrm{Hz}}}\$ input-referred noise levels and quite literally having to buy unpackaged dice and use wire-bonders and stable temps at \$-5\:^\circ\textrm{C}\$ [low, but not so low that my window would ice up] in tiny, sealed quartz-windowed modules in order to get there.)

These T-networks actually generate higher current noise (\$i_N\$) and the voltage divider at the output multiplies input offset voltage, drift, and amplifier voltage noise by the ratio of \$1+\frac{R_T}{R_G}\$. These input specifications are often pretty crappy anyway, so it quite quickly becomes insanely impractical to consider multiplying their already annoyingly high offset and drift (low input current FET opamps are almost always used here) by using a T-network instead of a big feedback resistor.

(Sure, the Johnson noise of the feedback resistor has to also be considered. But it's not nearly as much of a problem once you refer that back to the input as input current noise.)

---

NOTE to OP:

You wrote:

"Shouldn't the first \$R_T\$ and \$R_G\$ be in parallel, with the combination in series with second \$R_T\$? Resulting expression is \$\left(R_T\:\mid\mid\:R_G\right)+R_T\$. What is wrong with this expression?"

There is nothing wrong with that expression except that it's not shown within its proper context. Let's see where that goes.

Starting at the output and working backward:

$$\begin{align*} V_{TH} &= V_O\cdot\frac{R_G}{R_G+R_T}\\\\ R_{TH} &= \frac{R_T\cdot R_G}{R_G+R_T} \end{align*}$$

We now have to add the value of \$R_T\$ leading back to the inverting input node to \$R_{TH}\$ to get the total Thevenin resistance seen by the Thevenin voltage computed above. So, the current into the inverting node due to the output voltage of the opamp is:

$$\begin{align*} I_{V_O} &= \frac{V_{TH}}{R_{TH}+R_T} \end{align*}$$

But we are actually interested in the effective \$R_F=\frac{V_O}{I_{V_O}}\$ (the equivalent feedback resistance being determined by dividing the output voltage by the current it causes to enter into the inverting node, as if we had such a resistor there.) So:

$$\begin{align*} R_F &= \frac{V_O}{I_{V_O}}\\\\ &= \frac{V_O}{\frac{V_{TH}}{R_{TH}+R_T}}=\frac{V_O}{\frac{V_O\cdot\frac{R_G}{R_G+R_T}}{R_{TH}+R_T}}\\\\ &=\left(R_{TH}+R_T\right)\cdot\left(1+\frac{R_T}{R_G}\right) \end{align*}$$

And now, here, you can see your factor present in the above equation. But notice that it is not alone! There is a second factor there.

We could just stop there. But let's follow through:

$$\begin{align*} R_F &= \left(R_{TH}+R_T\right)\cdot\left(1+\frac{R_T}{R_G}\right)\\\\ &= \left(\frac{R_T\cdot R_G}{R_G+R_T}+R_T\right)\cdot\left(1+\frac{R_T}{R_G}\right)\\\\ &=\frac{R_T\cdot\left(R_T+2\cdot R_G\right)}{R_G}\\\\ &=R_T\cdot\left(2+\frac{R_T}{R_G}\right) \end{align*}$$

Which is just the same thing as before.

microcontroller - For variable voltage devices, namely SD cards, how much power do you save by using a lower voltage?

I'm designing a computer vision system and my 3 main components are

1. microcontroller (VDD = [1.8V, 3.6V])


2. microSD card (4 bit mode, VDD = [2.7V, 3.6V] according to SD 2.0 standard)


3. cheap cell phone camera (using the 8 bit parallel DVP interface, VDD = [1.8V, 3.0V], Vanalog = [2.6V, 3.0V])

I suppose using lower voltages will reduce power, but I'm starting to doubt this because I found all the components have an internal switched capacitor regulator that change the voltage further (1.3V for the microcontroller, 1.5V for the camera, and probably a high voltage for the microSD). So, using a lower voltage will just result in a higher current draw. The only exception is for the camera, whos datasheet says it uses a linear regulator to drop the external DOVDD (I/O voltage) to the 1.5V digital core. In that case, I can save (2.7V - 1.8V) * 0.1A = 90mW by using 1.8V instead of 2.7V. This is about a 15% power saving for the whole system.

Currently, I can get away with using 2.7V for all my components. I'm only working on this as a hobby and only have a 1 layer PCB, so I'm hesitant about using multiple voltages.

So my questions are:

1. 
   

   How much core/internal power does using a lower external voltage save? None?

   
   


2. 
   

   How much I/O power does using a lower voltage save? I'm aware from Bill Dally's presentations that data transfer often consumes more power than computation, but I'm not operating at GHz speeds. According to the camera data sheet, table 8-3, when you don't use the internal regulator for generating the 1.5V core voltage, the I/O current, Idd-do is only 9-12 mA, so using a lower swing wouldn't save much power.

   
   


3. 
   

   How do you use the 1.8V mode on SD cards? Initially, you need to operate at 2.7 - 3.6V. After sending a CMD5 requesting 1.8V, then you can drop to 1.8V. But this seems hopelessly complicated to me? That means I need to drop the voltage to the micro controller too, right? and do it gradually. Are there any regulators that allow smooth transitioning from 2.7V to 1.8V?

   
   
   

operational amplifier - How to produce sawtooth waveform from square waveform?

I have a question pertaining the changing of square waveform to sawtooth waveform using OpAmp.

Following the picture below, I have to create a sawtooth waveform from a square waveform.

It seems that I need to make the square waveform into the positive side of the sawtooth waveform. Then, use the same square waveform, give it a 180° phase shift and make it into another positive sawtooth waveform (180° from the first positive sawtooth waveform). Finally, use summing amplifier to combine them into a full positive sawtooth waveform.

Am I correct? If so, which opamp circuits (integrators, etc) should I use to make the square waveform to be the positive side of the sawtooth waveform?

Thank you for your time.

Answer

These circuits have been around almost forever. They are used in switching power circuits, old TVs, and pretty much anywhere PWM generated from a comparator might be in the mix.

There's probably a few good answers on this site, as well. For example, here is one.

I'm sure from your writing that you already pretty much know how. But for others (and to any degree it helps), I may as well state the approach in clear terms, first. The details are just a matter of implementing the plan. So here's the behavioral idea:

^{simulate this circuit – Schematic created using CircuitLab}

You mentioned the idea of a "summing amplifier" and this is handled perhaps better by using two differentiators based upon \$Q\$ and \$\overline{Q}\$, since these are easy to OR-together and then used to operate the reset switch. This way you only have one integrator and one resetting switch and you get the summing behavior at the output (with appropriate integrating capacitor and current source.

You can find many different opamp designs (including the above link I mentioned.) But let me give you something very simple that I used 35 or 40 years ago and still remember (kind of) well:

^{simulate this circuit}

This is a slow integrator, as shown, and assumes you have a low impedance square wave source. But it gets the idea across using concrete parts to make the point clear. I used a NOT gate (which could be implemented in a variety of ways) because I didn't know whether or not you have a \$Q\$ and \$\overline{Q}\$ of your square wave. (If not, that remaining behavioral element would need to be designed, as well.)

It's not difficult to work out these values. I didn't spent a lot of time working them out for the above schematic, but I can discuss my process.

1. To keep things simple I used the same capacitor value for all the capacitors. I selected \$4.7\:\mu\text{F}\$ for no particular reason.


2. The sharply rising pulse through \$C_1\$ and \$C_2\$ will have a very fast fall because the BJT base-emitter junction will snip it quickly.


3. We don't care about the sharply falling pulse through \$C_1\$ and \$C_2\$, but these will decay out via \$R_1\$ and \$R_2\$. Because this circuit is slow (\$5\:\text{Hz}\$), I only cared that \$5\,\tau\$ would be a quarter-period. With \$200\:\text{ms}\$ period, this meant that \$5\,\tau=50\:\text{ms}\$ or that \$\tau=10\:\text{ms}\$. Given the capacitor value, the resistor values for \$R_1\$ and \$R_2\$ were then easily derived.


4. I just picked a value for \$R_3\$ (not critical) that I felt would quickly remove charge. I didn't think about this much.


5. Given the use of a \$4.7\:\text{V}\$ zener, the collector shouldn't rise above about \$4\:\text{V}\$. I computed a maximum current source of \$I=C\frac{\text{d}V}{\text{d}t}=4.7\:\mu\text{F}\cdot\frac{4\:\text{V}}{100\:\text{ms}}\approx 190\:\mu\text{A}\$. The current-source is just a standard zener-based emitter follower one, set up to provide about \$\frac{4.7\:\text{V}}{33\:\text{k}\Omega}\approx 140\:\mu\text{A}\$. (You could use a current mirror, which would permit output peak voltages of the sawtooth that are closer to the rail.)

That's it. Have a look around the site and have a look at the other post here that I mentioned at the outset, too.

---

I decided to put this schematic into LTspice, today. So I'll post up the results of it.

Here's the full schematic as entered into LTspice:

And here's the input and output waveforms:

Simulated, it is very close to my expectations and it does show that the premise is appropriate to the problem. The rest is a matter of improving on the details related to specific circumstances.

resistors - Side effects of using large resistances

Are there any problems that can be caused by using resistors of large resistances (in the order of megaohms)?

I'm designing a feedback network that is just a voltage divider, and I want the feedback to drain as little current as possible from the circuit. The only thing that matters is the ratio between the resistors. So my question is: is there any reason why one would pick, for example, resistors of 1 and 10 Ohms instead of 1 and 10 MOhms?

Answer

There are many drawbacks to both low and high values alike.

The ideal values will fall in between very large and very small for most applications.

A larger resistor of same type will, for example, create more noise (by itself and through small induced noise currents) than a smaller one, though that may not always be important to you.

A smaller resistor will drain more current and create more losses, as you have surmised yourself.

A larger resistor will create a higher error with the same leakage current. If your feedback pin in the middle of your resistors leaks 1 μA when the resistor feeding that leak is 1 MOhm, that will translate to an error of 1V, while a 10k resistor will translate to an error of 10mV.

Of course, if the leakage is in the order of several nA or less, you might not care much about the error a 1 MOhm resistor creates. But you might, depending on what exactly you are designing.

Smaller resistors in feedback systems, e.g. with inverting amplifiers using op-amps, may cause errors on the incoming signal if the incoming signal is relatively weak.

It's all checks and balances, and if that's not enough information at this point, you might want to ask a more direct question about specifically what you are doing. With schematics and that.

oscilloscope - Wrong measurement of DSO-5200A?

I'm using a DSO-5200A from Voltcraft and noticed the voltage measurement represented incorrectly (it is doubled).
Any ideas how to reset this?

Channel 1 (green) measures a (noisy) 5V and has a Vmean measurement of 10V.
Channel 2 (yellow) measures the DSO's own calibration square wave. Frequency is measured correctly, but the mean value is again wrong.
The cursors correctly indicate a voltage difference of 2V.