I have a text file named "Hex_data.txt". I want to load content of Hex_data.txt into a variable name RAM in verilog. When I try this, I get an error that the text file can't be found. Where is this file loaded from?
The content of "hex_data.txt" :
21
a4
2a
26
7a
ff
6f
I want to create a variable name "RAM" defined like:
reg [6:0] RAM; in which the above content save like:
RAM[0]=21
RAM[1]=a4
RAM[2]=2a
RAM[3]=26
RAM[4]=7a
RAM[5]=ff
RAM[6]=6f
I wrote a code:
module file_read;
reg [7:0] RAM [0:6];
initial $readmemh("Hex_data.txt", RAM);
integer i;
initial begin
$display("data:");
for (i=0; i < 7; i=i+1)
$display("%d:%h",i,RAM[i]);
end
endmodule
But the above code not working. How can i get desired output?
Answer
Xilinx presented this use case in the Synthesis User Guide for Vivado UG901 on page 126. This example also works for the Xilinx ISE tool chain, but I don't know the User Guide number.
The essential part of code is this:
reg [31:0] ram [0:63];
initial begin
$readmemh("rams_init_file.data", ram);
end
There are two read functions:
- $readmemb -> binary
- $readmemh -> hexadecimal
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