problem assigning a zero-length array port in vhdl

I have a vhdl component with a custom type defined for a port. The type is an array of a composite record type. The array size is adjustable via generic and according to the person who designed the component, I can set it anywhere from zero to eight. I would like to set the size to zero to disable it but I'm having trouble getting it to synthesize because I cannot find an acceptable way to assign the input ports.

So how do I assign a zero-length input vector on a component instantiation?

Below are some code snippets of what I have to aid with understanding my question.

Type declarations:

type axi_out_type is record
    aready : std_logic;

end record axi_out_type;

type axi_out_vector is array (natural range <>) of axi_out_type;

type axi_in_type is record
    wid    : std_logic_vector(3 downto 0);
    wdata  : std_logic_vector(1023 downto 0);
    wstrb  : std_logic_vector(127 downto 0);
    wlast  : std_logic;
    wvalid : std_logic;

end record axi_in_type;

type axi_in_vector is array (natural range <>) of axi_in_type;

Component declaration:

component my_component is
generic(
    ...
    NB_AXI_SLV: in integer range 0 to 8 := 1;
    ...

);
port(
    ...
    axi_in_ports: in axi_in_vector(NB_AXI_SLV-1 downto 0);
    axi_out_ports: out axi_out_vector(NB_AXI_SLV-1 downto 0);
    ...
);

signal my_axi_in : axi_in_type;

Component instantiation:

comp: my_component
generic map(
    ...
    NB_AXI_SLV => 0,
    ...
)
port map(
    ...
    axi_in_ports => (others => my_axi_in),  --What do I assign here?!?!

    axi_out_ports => open,
    ...
)

my_axi_in <= (wid=>(others => '0'),wdata=>(others => '0'),
                wstrb=>(others => '0'),wlast=>'0',wvalid=>'0');