digital logic - What is the beginning state for Q in a SR latch?

In this diagram

what would be the beginning state for Q? Since the first NOR for S and R rely on previous results, there must be something for the first iteration?

NOTE: I'm in a first year digital logic class, so the question is for theoretical use (table making, various homework problems it applies to, etc.), not actual implementation. Just for things like "if R is __ and S is __ what is Q?" Simple things like that.

Answer

If you just powered that on, the initial state would be the outcome of a race condition, depending on which gate output can become high first. In actuality, one gate or the other would tend to have a faster rise time, so it probably would tend to come up in one state or the other, but there'd be no guarantee.