verilog - What is the purpose of pre-synthesis simulation?

I have used Verilog to develop RTL representations of synthesizable digital circuits, and have recently been using Verilator to run simulations of these. My understanding of Verilog semantics, therefore, is based on how things work under those simulations (Verilator attempts to match a synthesized representation).

However, this question on StackOverflow (see also this linked document) has drawn my attention to the idea that Verilog can legitimately be run in two different modes, these being pre-synthesis and post-synthesis, and that the meaning of the language (and the results of simulation) are not the same between the two modes. Of particular interest to Q&A sites like this one, discussions about Verilog's behavior might become quite confused by lack of an explicitly specified distinction between the two modes.

I am aware that Verilog can be used to describe algorithms in ways that cannot be readily synthesized by automated tools, but assuming we have a design that is targeted for synthesis, what would be the purpose of running a pre-synthesis simulation?

Note: What actually started me wondering about this was this response to another question that I posted. I was interested in post-synthesis semantics, but the answer seems to be addressing pre-synthesis semantics, although the distinction is not explicitly indicated in the question or the answer.

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I understand that the physics and timing of real hardware is not addressed in pre-synthesis simulations, but this is not what I am asking about.

An example of language semantics differences (as indicated in the linked document):

• pre-synthesis: the order of blocking assignments can matter


• post-synthesis: the order of blocking assignments does not matter

The point being, pre-synthesis simulation may fail to match hardware due to semantic rules -- even if there are no problems in the timing. So running a pre-synthesis simulation may give the wrong result (one that doesn't match hardware) unless you have carefully constructed the code such that it will work the same for both modes of the language. So the question is basically, why run a simulation that is known to have wrong semantics.

Further note: Verilator is completely idealized, and has no notion of any specific hardware, so perhaps it is not accurate to call that post-synthesis. However, it uses the semantic rules of post-synthesis, and is purportedly very fast, so to me this establishes a baseline of what first-order simulation should probably do.