xilinx - vhdl port declaration with different sizes

I'm writing a vhdl model and I'm stuck with a problem about port declaration. Let's say that I have an entity entityA that instantiates N entityB. Now, entityB has a port, out, with size M bits, and M can vary among all entities, so out is std_logic_vector(M-1 downto 0). These ports need to be propagated outsize entityB.

If all entityB components would have the same port size, say FIX_M, the solution would be to use a std_logic_vector(N*FIX_M-1 downto 0) in entityA. My problem is that the size M can vary. The first solution that comes to my mind is to use the same solution, using instead of M a MAX_M, but in that case a lot of pins would be left unused (and for input it is a problem, right?).

Do you have a better idea? Thank you in advance.

Answer

It uses an array of sizes to specify the individual sizes of EntityB. The port of EntityA has the size calculated by sum.

The matching bits are sliced by high and low.

global function:

function sum(SIZES) is
  variable count : integer := 0;

begin
  for i in SIZES'range loop
    count := count + SIZES(i);
  end loop;
  return count;
end function;

Example:

entity EntityA is
  genierc (

    SIZES : integer_vector
  );
  port (
    data(sum(SIZES) - 1 downto 0)
  );
end entity;

architecture rtl of EntityA is
  function high(SIZES, idx) is
  begin

    for i in 0 to idx loop
      pos := pos + SIZES(i);
    end loop;
    return pos - 1;
  end function;
  function low(SIZES, idx) is
  begin
    for i in 0 to idx - 1 loop
      pos := pos + SIZES(i);
    end loop;

    return pos;
  end function;
begin
  genB : for i in SIZES'range generate
    instB : entity work.EntityB
      generic map (
        N => SIZES(i)
      )
      port map (
        data => data(high(SIZES, i) downto low(SIZES, i))

      );
end architecture;

Usage:

signal input : std_logic_vector(13 downto 0);

ex : entity work.EntityA
  generic map (
    SIZES => (2, 3, 4, 5)
  );

  port map (
    data => input
  );