VHDL that can damage FPGA

I read somewhere that bad VHDL code can lead to FPGA damage.

Is it even possible to damage a FPGA with VHDL code? What kind of conditions would cause this and what are the worst case scenarios?

Answer

Adding to @Anonymous's answer, there are designs you can build which can damage the fabric of an FPGA.

For starters if you build a very large design consisting of huge quantities of registers (e.g. 70% of the FPGA) all clocked at nearing the FPGAs maximum frequency, it is possible to heat the silicon considerably. Without sufficient cooling this can cause physical damage. We lost a $13k FPGA because it overheated due to the dev-kit having a terrible cooling system.

Another simpler case can be combinational loops. For example if you instantiate three not gates chained together in a ring, and disable or ignore the synthesizers warnings about such a structure, you can form something which is very bad for an FPGA. In this example you'd make a multi-GHz oscillator which could produce a lot of heat in a very small area, probably damaging the ALM and surrounding logic.