When to use STD_LOGIC over BIT in VHDL

Whats the difference between using:

ENTITY MyDemo is 
    PORT(X: IN STD_LOGIC; F: OUT STD_LOGIC );
END MyDemo; 

and

ENTITY MyDemo is 
    PORT(X: IN BIT; F: OUT BIT );
END MyDemo; 

What are the limitations of using BIT over STD_LOGIC and vice-versa? Are they completely interchange able? I understand that if I've define STD_LOGIC I can't use it with a BIT_Vector to access the elements in the array. But I can't seem to see the difference.

Answer

Bit is a predefined type and only can only have the value 0 or 1. The Bit type is an idealized value.

type Bit is ('0', '1');

std_logic is part of the std_logic_1164 package and provides more realistic modeling of signals within a digital system. It is capable of having nine different values. Typically within your code you will only use 0, 1, and Z (High-Z). But U (Uninitialized) and X (Unknown) are also very useful when modeling the system in a testbench.

    -------------------------------------------------------------------    
    -- logic state system  (unresolved)
    -------------------------------------------------------------------    
    TYPE std_ulogic IS ( 'U',  -- Uninitialized
                         'X',  -- Forcing  Unknown

                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance   
                         'W',  -- Weak     Unknown
                         'L',  -- Weak     0       
                         'H',  -- Weak     1       
                         '-'   -- Don't care
                       );

--    attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";


    -------------------------------------------------------------------    
    -- *** industry standard logic type ***
    -------------------------------------------------------------------    
    SUBTYPE std_logic IS resolved std_ulogic;

The std_logic_1164 package also provides conversion functions to convert std_logic to Bit.