Sunday, 5 November 2017

transistors - How not to waste power with digital inputs?


I am trying to make simple gates with n-MOSFETS, yet I'm not sure how to actually do physical gate inputs correctly.


At first, I tried this (a single-pole, single-throw switch from +5V to gate). However, as I learned recently, this is bad because when the switch is open the gate has a floating voltage.


So then, I thought that I should use a pull-down resistor from gate to ground, and then have a switch from +5V to gate, like this. However, this is undesirable because the pull-down resistor always draws 25mW and has a constant current of 5mA, which seems to me like a huge waste of power and current (especially as I am using USB power, and thus have a max current of 500mA for the entire circuit, which will consist of many more transistors and inputs). Note that I cannot have a very large pull-down resistor, or the transistor stops working correctly, which means that I need to have a small resistor, and thus a large current and power draw.



My next thought was to not use a pull-down resistor, and instead use a single-pole, double-throw switch between power, ground, and gate, like this. This seems to me like the best way to have digital inputs, because there is no constant power drain. However, I would need to buy some of these switches since I don't have any right now.


My question is the following: how do existing circuits (such as those found in my computer) do physical digital inputs? Do they have pull-down or pull-up resistors and waste power and current, or do they even follow any of the methods that I thought of? Is there a better way of doing this that I haven't thought of?



Answer



For the record, here's one of the circuits you tried:


enter image description here


Your problem is connecting the load to the source of the FET rather than the drain. Tie the source directly to ground, and connect the load between 5 V and the drain:


schematic


simulate this circuit – Schematic created using CircuitLab


Now nearly all of the supply voltage can be applied to the load. In your proposal, the FET is working as a source follower, in which the FET will operate in saturation mode rather than fully switched, and voltage at the load is likely to be 2 or 3 V below the supply voltage.


If you want to have a high-side switch instead of low-side, use a PFET instead of NFET.



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