EDIT: This has been repeated several times, so putting it on top: Yes, it is well known that there is no "standard" for I2C inter-device connectors, but surely this community can formulate a list of "guidance" points for making such interconnects, based on signal behavior, noise minimization, and mitigation of risk due to wrong connections.
NXP defined the I2C standard without specifying a pin-out for I2C connectors, is my understanding. The only guidance from NXP seems to be a mention of placing a Ground and / or Vss between SDA and SCL if Vss / Gnd are carried across the interconnect.
Purchases of various I2C modules has left me with a variety of I2C pin-outs, and a bit of a task keeping track of the various little ribbon-cable-switching shims I've had to make for them.
e.g.
- Mono OLED module: SCL, SDA, GND, 5V (obviously not ideal, since clock and data are next to each other.
- Sensor Shield for Arduino: SDA, SCL, GND, 5V (again not ideal, plus switched SCL/SDA)
- Color LCD module: SCL, GND, 5V, SDA (Yay!)
- No-name I2C repeater: SCL, 5V, GND, SDA (ouch, they switched power pins! Nearly let the magic smoke out.)
So my question is this:
Is there a definitive / authoritative guideline for the I2C 4-pin connector pin-out sequence to use, where both Vss and GND are to be carried from host to device?
Failing this, is there any directory, however incomplete, of I2C modules / devices listing the pin-out each has adopted?
Clarification: Looking for guidelines such as "put Vss closer to SCL because..." rather than a defined standard which clearly does not exist.
Answer
I've recently rolled my own as far as I2C connectors go. The connector itself is not very important, right now I'm just using 100mil pitch header (usually female on board so it's not so pokey when not connected), but any 4plus pin connector will do. Additionally, I'm using the P82B715 from TI as an I2C bus extender. This overcomes the capacitance issues associated with running long I2C drops off board, which as people have been saying, I2C was not intended for initially. I did try many different combinations, like in the examples you gave and I noticed absolutely no difference in performance. I believe this is because I2C is relatively slow, interference between SDA and SCL is not much of an issue. Basically the rise time for voltages (when interference will occur) on the bus are much much smaller than a bit length. So, that may not be what you want to hear, but it does afford more options. Personally I went with [VCC, SDA, GND, SCL] to be easily routed to/from this chip and also be immune to a VCC/GND mix up when plugged in backward.
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