real to std_logic_vector in VHDL

I have trouble understanding conversion between different data types in VHDL and needed help with conversion to `STD_LOGIC_VECTOR' type in VHDL.

I want the code below to be synthesized such that it can be used on real hardware.

For now i have the code setup as follows

signal   VREF  : real := 65536/3.3;
constant SIG   : real := 2.33;

signal TEMP    : unsigned(15 downto 0);

signal WORD_A : STD_LOGIC_VECTOR(23 downto 0) ;
signal SIG_A  : STD_LOGIC_VECTOR(15 downto 0);

BEGIN

TEMP <= to_unsigned(VREF,16)*to_unsigned(SIG,16);
SIG_A <= STD_LOGIC_VECTOR(TEMP);
WORD_A <= "00110000" & SIG_A;

I used the following libraries : IEEE_NUMERIC_STD.ALL, IEEE.MATH.REAL

I get the following error ERROR: [VRFC 10-1471] type error near VREF ; current type real; expected type natural

Any inputs is appreciated

Thanks