verilog - What exactly do we write in a test vector?

My professor has asked me to write Test vectors for the controller shown in the circuit below:

We have not implemented the controller as of now. I want to understand what exactly we write in a test vector. Is this merely all the possible permutation and combination of inputs? For an AND gate I can write test vectors very easily:

Reg A;

Reg B;

   A B
1- 0 0
2- 0 1
3- 1 0
4- 1 1

But in the present case I am having different scenarios:

1- BLANK =1, CLOCK=1 (some signals defined in spec of the chip TLC5944)


{




}


2- BLANK =0, CLOCK=1


{



}

and so on.

Is this the correct approach to write test vectors? Can anybody please suggest me what are the best practices for writing test vectors? and what exactly we write in a test vector?