transistors - Implementation of NAND gate

The image below shows a extremely simplified circuit diagram. I do understand the logic behind that. However, the other image(below) is the one i dont understand. It shows a circuit diagram implementing the NAND gate. I do understant how the NAND gates works. However i dont understand the circuit on the left of the image. The truth table shows the correct output of a NAND gate, however, based on the circuit diagram on the left of the image, if A and B is 0 shouldnt the output for Y be 0 as well. I dont understand the symbol beside the Alphabets as well. I dont know how the current in the circuit diagram is flowing as well. Would anyone care to explain how this works? Thank you.