transistors - The detailed working steps of the DRAM 3T1C cell?

This question is related to this one. But the focus is a little different so I put it here.

I tried to understand the detailed working steps of below circuit. It is an old 3T1C DRAM cell circuit. This picture is quoted from the book Memory Systems by Bruce Jacob.

I think the input capacitance of T2 is just a representation of the T2's characteristic, which is not a real capacitor. I know that conceptually capacitance is defined as the ratio of q/V.

My first 2 questions are:

• 
  

  Does this input capacitance of T2 mean the ratio between the charges q and voltage V required to open T2's gate?

  
  


• 
  

  If the charges remain on T2, will T2's gate stay open?

  
  
  

Below is my understanding of the circuit steps:

I guess:

• 
  

  write rowline is active-high

  
  


• 
  

  read rowline is active-high

  
  
  


• 
  

  write bitline is active-high

  
  


• 
  

  read bitline is active-low

  
  

Steps to Write and Read "1" to and from the cell

Steps:

1. 
   

   write rowline goes to high to signal the write operation. T1 is opened.

   
   


2. 
   

   write bitline goes to high because we are writing 1.

   
   


3. 
   

   write bitline reaches T2 through T1. T2 is charged and opened.

   
   



4. 
   

   write rowline goes to to low to finish the writing. T2 is charged and opened.

   
   


5. 
   

   read rowline goes to high to signal the read operation. T3 is opened.

   
   


6. 
   

   read bitline reaches T2 through T3.

   
   


7. 
   
   

   Because T2 is opened in 3, 4, so read bitline further reaches ground through T2. So read bitline reads 0 (ground).

   
   


8. 
   

   Because read bitline is active-low, so the 0 voltage in 7 is interpreted as a logical 1.

   
   

Steps to Write and Read "0" to and from the cell

Steps:

1. 
   
   

   write rowline goes to high to signal the write operation. T1 is opened.

   
   


2. 
   

   write bitline goes to low because we are writing 0.

   
   


3. 
   

   write bitline reaches T2 through T1. T2 is not charged or opened.

   
   


4. 
   

   write rowline goes to to low to finish the writing. T2 is not charged or opened

   
   
   


5. 
   

   read rowline goes to high to signal the read operation. T3 is opened.

   
   


6. 
   

   read bitline reaches T2 through T3.

   
   


7. 
   

   Because T2 is not opened in 3, 4, so read bitline reads the voltage of read rowline through T3, which is high.

   
   



8. 
   

   Because read bitline is active-low, so the high voltage in 7 is interpreted as a logical 0.

   
   

Am I correct?