mosfet - Gate capacitance vs. Gate charge in n-ch FETs, and how to calculate power dissipation during charging/discharging of the gate

I am using a MOSFET driver (TC4427A), which can charge a 1nF gate capacitance in about 30ns.

The dual N-ch MOSFET I am using (Si4946EY) has a gate charge of 30nC (max) per fet. I am only considering one for now as both on the die are identical. I am driving the gate to 5V. (It is a logic level fet.)

Does this mean I can apply Q = CV to work out the capacitance? C = 30nC / 5V = 6nF. So my driver can turn the gate fully on in about 180ns.

Is my logic correct?

Gate resistance of the MOSFET is specified at a max. of 3.6 ohms. Will this have any effect on the calculations above? The driver has a 9 ohm resistance.

Is there any significant difference for when the gate is discharged instead of charged? (turning off the fet.)

As a side question, during the 180ns the fet is not fully on. So Rds(not-quite-ON) is quite high. How can I calculate how much power dissipation will occur during this time?