vlsi - PullUp and PullDown Network in CMOS

How exactly pullUp and pullDown Network in CMOS should be defined... I mean why "PullUP" or "PullDown"? And why PMOS in pullUp network and NMos in Pulldown network?Why not Pmos in pullDown and Nmos in PullUp?

Answer

PullUp and PullDown

Pullup - a network that provides a low resistance path to Vdd when output is logic '1' and provides a high resistance to Vdd otherwise.

Pulldown - a network that provides a low resistance path to Gnd when output is logic '0' and provides a high resistance to Gnd otherwise.

What if PMOS is used in pullDown and NMOS in PullUp?

If we use PMOS in pull down network, then its gate terminal should be provided with a negative voltage. Similarly if we use NMOS in pull up network, then its gate terminal should be provided with a voltage that is more positive than Vdd.

So the voltages corresponding to logic states at input are different from that at output. Hence two such 'CMOS' gates can not be interfaced directly.

In other words, \$V_{OH} < V_{IH}\$ and \$V_{OL} > V_{IL}\$ which will result in negative noise margin. And hence this logic family would be incompatible with itself.