flipflop - Metastability error propagation with flip flop

I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain crossing boundaries, but my confusion is that the output of metastability is unpredictable, it might lead to high or low level, and that output then will be propagated to the rest of the circuit, so how can the second or the third flip flop catch the right value to be transmitted , if the first flip flop is always at metastable state and might settle in a wrong level ?