What is this operator called as "+:" in verilog

I am going through verilog test case and found a statement

assign XYZ = PQR_AR[44*8 +: 64];

What does "+:" operator be known as. I tried to find this on google but didn't get any relevant answer.

Answer

That syntax is called an indexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant.

Example from the SystemVerilog 2012 LRM:

logic [31: 0] a_vect;
logic [0 :31] b_vect;

logic [63: 0] dword;

integer sel;

a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]

dword[8*sel +: 8] // variable part-select with fixed width