Why do ATmega (e.g. 328P or 644P) have CKDIV8 (or CLKPS = 0011) factory programmed along with a default internal 8 MHz oscillator?
From the 644P documentation: 6.12.2 CLKPR - Clock Prescale Register, Page 40:
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. [...] The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Is it just a precaution to ensure the CPU clock does not exceed say a 16 MHz limit when configuring the MCU to run with an external oscillator of too high frequency (and forgetting to change CLKPS accordingly). Or are there other reasons?
Answer
Note the dependency of the maximum allowed clock speed on the supply voltage: E.g. the 644PV can only reach 4 MHz when running at 1.8V (similar for other chips)
If the controllers were programmed to a default 8 MHz you could not program them in a circuit running at such low supply voltage. 1 MHz is a safe default frequency that any AVR can reach at any supply voltage within its specifications.
You could change the internal oscillator to a 1 MHz one and leave the clock divider unprogrammed, but this forbids to run the controller at a higher clock rate without an external clock source.
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