i am interfacing a system, this system output signal of 200ns digital pulse with repetition time of every 3ms. Ideal voltage of signal would be 0v to 3.3V but signal coming from system have high overshoot and undershoot value (value upto +5 to -2V). and i want to interface this signal with Xilinx 7 series FPGA(artix) with bank voltage of 3.3V. Attach is signal shape i get from system.
- So first question is If i don't put any protection circuit would my IO pin of FPGA will burnout or what will happen. as maximum voltage limit as per 7 series FPA for 3.3V bank is -0.5 to 3.8V.
- Second question is what will be good protection circuit for this overshoot and undershoot protection.
- is there any recommended OPAMP IC which will handle 200ns pulse easily
I need circuit which will handle 200ns pulse easily.
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