vhdl - Conversion from fixed point to IEEE 754

I am trying to design a simple processor (in VHDL) that takes in its input a real number coded in the fixed point representation in 2's complement (10 bits for the integer part, and 6 for the fractional part), and outputs its IEEE 754 single-precision format equivalent:

I have been searching for a while now, and still couldn't find any resources on this type of conversion, at least some flow chart from which I could start.

Answer

Basically, you do four things:

• convert from 2’s complement to signed magnitude, save the sign


• count leading zeroes (find first ‘one’)



• add a bias to that to make the exponent


• shift the integer to normalize it as the mantissa.

About four lines of code that synthesizes to some logic, an adder, and a shift mux.

EDIT: As Tim said, before you do all that you also need to convert the 2’s complement integer to signed magnitude. So one more line.