digital logic - A simple clarification on latches and flip-flops

Here are two representations of a gated SR latch (first one from my book and the second one from Wikipedia):

The part I don't understand are the S and R inputs, why are they reversed in these two pictures?

Answer

The two are different because the first doesn't show the internal structure of the SR latch, and it is hooked up in reverse of the second example. The first example is concerned entirely with the logic of the latch, while the second is concerned with the gate connectivity.

That is, in both cases, a high enable, a high set and a low reset will both cause Q to go high. It's just that, in the first example the set input and Q output are at the top, and a high at the top input will cause a high on the top output. Most beginners find this sort of organization easier to understand. In the second case, a high on the top input will cause the bottom output to go high. When you show all the gates, it's easy enough to see how this works, but it's less spatially intuitive. If it helps, the complete circuit for the first example is

^{simulate this circuit – Schematic created using CircuitLab}