How to calculate the required number of FPGA logic elements?

I have a Lynxmotion hexapod which uses hobby servos for each of its 18 degrees of freedom (DOF).

The basic problem with this is that I cannot get data on the joint angles. I have modified the servos so that I can measure their orientation via the signal from the pot. For each DOF I want to read in the orientation of the servo via ADC and use a PID controller to generate the appropriate PWM signal. This works simply enough with an Arduino for one servo.

Unfortunately I have not found any microcontrollers with 18 10 bit (or higher) timers capable of generating PWM and 18 ADC. As such I am exploring the idea of using an FPGA. Specifically I'm considering the Papilio Pro FPGA. In reading about it I see that it has around 500,000 logic elements. While I'm new to FPGA I'm guessing this is the most crucial metric for my needs (if I'm wrong, please feel free to correct me).

The question in my mind is, how many logic elements do I need for my application? Are there any good rules of thumb for such calculations?

Answer

For several years, FPGA vendors haven't really advertised "equivalent logic gates", because it's a very poor metric for how much functionality can be achieved in a given FPGA.

To get a more complete picture of what's available in the Papilio, you want to look at this table from the Spartan 6 Family Overview:

According to the Sparkfun page you linked, the device on the Papilio is the XC6SLX9, the second row in the table.

In a system like you're describing, the limiting resources are likely to be the flip-flops. It's fairly straight forward, once you start thinking about your design in detail, to work out how many flip-flops are required. Given 11,000 flip-flops, you should easily be able to manage 18 counters and control logic.

Another resource to look out for is I/O. With 18 10-bit ADC's you'll probably either need to use a serial interface to connect to them, or a multiplexed parallel interface. You'll also want to make sure that the Papilio board pins out enough of the I/O pins, and that they accessible I/O's can be selected to the voltage levels you need (which may require digging in to the Papilio documentation or the datasheet for the specific S6 device you're using).

If you were designing a microcontroller or doing DSP-type functions, the block RAM or DSP slices could be the limiting resource, but I doubt you'll have problems with those in your project.