fpga - How can I implement a simple, Q only, D-latch using VHDL?

I just started VHDL today and I'm the type of person that can only learn by doing stuff, so after I made some basic gates in VHDL, I tried making a simple D-latch(so no clock signal), however without success. I get all kinds of errors such as in1 not defined, std_logic not defined, etc.

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity dflip is

end dflip;

architecture structural of dflip is

    component AND2
        port (in1, in2:in std_logic; out1: out std_logic);
    end component;


    component OR2
        port (in1, in2:in std_logic; out1: out std_logic);
    end component;

    component NOT1
        port (in1: in std_logic; out1: out std_logic);
    end component;

    signal D, E, E_NOT, Q, OUT_AND1, OUT_AND2: std_logic;


begin   
    U0: NOT1    port map (E, E_NOT);
    U1: AND2    port map (E, D, OUT_AND1);
    U2: AND2    port map (E_NOT, Q, OUT_AND2);
    U3: OR2     port map (OUT_AND1, OUT_AND2, Q);
end structural;


entity NOT1 is

    port (in1: in std_logic; out1: out std_logic);
end NOT1;

architecture behavioral_not of NOT1 is
begin
    out1 <= not in1;
end behavioral_not;


entity AND2 is

    port(in1, in2: in std_logic; out1: out std_logic);
end AND2;

architecture behavioral_and2 of AND2 is
begin

    out1 <= in1 and in2;

end behavioral_and2;



entity OR2 is
    port (in1, in2: in std_logic; out1: out std_logic);
end OR2;

architecture behavioral_or of OR2 is
begin
    out1 <= in1 or in2;
end behavioral_or;

I made it structural, because I could not make it to work behavioral, because it seems I cannot use if statements if I write behavioral(makes sense). The problem is with that Q output which needs to be connected back to the input of an AND gate.

So how do I do this?

Answer

Latches and flip-flop can't be modeled with logic gates in VHDL, this is for analog simulators only! The feedback logic doesn't bode well with the VHDL simulator. Furthermore, no synthesiser would recognize it as a latch/flip-flop.

To instantiate a latch/flip-flop, you can either instantiate your vendor's primitives or use this generic code:

LATCH: process(en, d)
begin
    if en = '1' then
        q <= d;
    end if;

end process LATCH;

DFF_ASYNC: process(rst, clk)
begin
    if rst = '1' then
        q <= '0';
    elsif rising_edge(clk) then
        q <= d;
    end if;
end process DFF_ASYNC;


DFF_SYNC: process(clk)
begin
    if rising_edge(clk) then
        if rst = '1' then
             q <= '0';
        else
             q <= d;
        end if;
    end if;

end process DFF_SYNC;

Use logic gates for combinational circuits only. If you want a challenge, you may be better with simulating ALU logic then synchronous elements. As a final note, keep in mind that using logic gates to design circuits is reserved for masochists, most VHDL designer use higher level construct that are easier to read and to debug.

Update

Apparently, latches can be simulated in VHDL using logic gates (thanks @David Koontz). Look at his answer to see how!