I would like to ask some help to better understand limitations of multi-project wafer services (MPW).
In nutshell, i found about the service, that it merges many projects on wafer, so one project only have to pay for a share of its surface. While it is easy to understand, that i pay only for 100 mm2 of an area of 70000 mm2 so it costs less, i nowhere found to mention, that asic projects may have different amount of layers for their design. Number of layers could be anywhere from 6 to 35 and even more. If i need for example 30 layers for my design, and there are only projects with demand of 15..20 layers, how an MPW service can merge my project with cost effectivity? Can it do that at all?
I dont know, if my question involves any industrial secret or not, tell me if i was that careless.
I will be happy with any reference to internet blogs, e-docs, books or anything about the question.
Answer
I highly doubt you're making something more complicated than the Alpha 21064 CPU, and so I highly doubt you really need more than the 3 metal interconnect layers that was used by that CPU.
It sounds like you think that every chip designer arbitrarily uses however many layers they feel like using this week, and then later the fab does whatever it takes to make that happen.
In theory, yes -- a fab could theoretically accept a chip design that requires 9 metal interconnect layers plus a few chip designs that requires fewer layers, and the fab could more-or-less automatically insert vias and metal to pass signals through the "skipped" layers of the simpler chips up to the top bonding pad layer, and fabricate all those designs on the same wafer.
In practice, what happens is that the chip designer (like a PCB designer) asks the fab what their capabilities and for the design rules for that process. Typically a fab has a few different processes, each one with its own dedicated production line. One process is least expensive and simple with few layers and large, slow transistors. Another process is most expensive with more layers (but still far fewer layers than AMD's fab) and smaller linewidths that can be used to fabricate faster transistors. Often there is no one "best" process -- there's one high-speed process that can't handle high voltages; there's a separate high-voltage process that's really slow; etc.
The production line has already been set up with a certain number of layers of a specific kind. If you want more or different layers, you have to go to a different production line. If a chip needs to be high-speed and high-voltage and high-density, even if each one is within the capabilities of one or another of the fab's production lines, we still risk not being able to fab your chip at all because none of the available lines can handle that specific combination.
The chip designer (like a PCB designer) picks a process before even starting to lay out the chip and tries very hard to keep the design within the capabilities and design rules of that process.
If the chip designer finds the chip doesn't really need all the capabilities of that process, then the chip designer manually adds vias and metal to pass signals through the "skipped" layers. (And meanwhile seriously considers switching to a lower-cost process).
It would be nice if you could simply download that capability information from the fab's website. But in practice the chip designer needs to sign a confidentiality agreement (CDA) and work with some university professor who already knows how to shepherd student chip designers through the process.
So, for example, Europractice requires signing a non-disclosure agreement (NDA), filling out an application and fax it back (!), etc., etc.
So, for example, the I3T80 Process available through MOSIS page describes how to get the capabilities and design rules for that process -- get an account with MOSIS; sign a confidentiality agreement, etc., etc. That process is one of the standard foundry processes at On Semicondustor who publishes the I3T80: 0.35 um Process Technology datasheet.
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