Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

I have a vivado project containing a Xilinx IP core. A tcl script was generated for this project and contains links to the IP core source. The .tcl script and IP source files (xml, xci and veo files) have been added to version control.

When I run the TCL script to create the project, it works fine. However, right-clinking on the IP in vivado and selecting "generate output products" in order to generate the synthesis files produces the following error:

[Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

Deleting and re-adding the IP files doesn't fix the issue.

How do I use the tcl script to include and regenerate IP sources?