vhdl - How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a number of EDA tools that provide a graphical design browser for your RTL.

What tools area available to draw schematics programmatically either from a verilog or vhdl definition, or from some other text-based input format?