digital logic - Why do we use negative edge trigger Flip Flop instead of positive edge triggered?

The glitches due to race condition can be avoided by using a negative-edge triggered flip-flop instead of the positive-edge-triggered flip-flop used.

What does this mean?

Source: http://www.zeepedia.com/read.php?the_555_timer_race_conditions_asynchronous_ripple_counters_digital_logic_design&b=9&c=26